connect progress signal directly to the logger.
[Rockbox.git] / firmware / export / sh7034.h
blob242e5687f1fe17db91f630fb65a339d482172599
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2002 by Alan Korr
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
18 ****************************************************************************/
20 #ifndef __SH7034_H__
21 #define __SH7034_H__
23 #define GBR 0x00000000
25 /* register address macros: */
27 #define SMR0_ADDR 0x05FFFEC0
28 #define BRR0_ADDR 0x05FFFEC1
29 #define SCR0_ADDR 0x05FFFEC2
30 #define TDR0_ADDR 0x05FFFEC3
31 #define SSR0_ADDR 0x05FFFEC4
32 #define RDR0_ADDR 0x05FFFEC5
33 #define SMR1_ADDR 0x05FFFEC8
34 #define BRR1_ADDR 0x05FFFEC9
35 #define SCR1_ADDR 0x05FFFECA
36 #define TDR1_ADDR 0x05FFFECB
37 #define SSR1_ADDR 0x05FFFECC
38 #define RDR1_ADDR 0x05FFFECD
40 #define ADDRAH_ADDR 0x05FFFEE0
41 #define ADDRAL_ADDR 0x05FFFEE1
42 #define ADDRBH_ADDR 0x05FFFEE2
43 #define ADDRBL_ADDR 0x05FFFEE3
44 #define ADDRCH_ADDR 0x05FFFEE4
45 #define ADDRCL_ADDR 0x05FFFEE5
46 #define ADDRDH_ADDR 0x05FFFEE6
47 #define ADDRDL_ADDR 0x05FFFEE7
48 #define ADCSR_ADDR 0x05FFFEE8
49 #define ADCR_ADDR 0x05FFFEE9
51 #define TSTR_ADDR 0x05FFFF00
52 #define TSNC_ADDR 0x05FFFF01
53 #define TMDR_ADDR 0x05FFFF02
54 #define TFCR_ADDR 0x05FFFF03
55 #define TCR0_ADDR 0x05FFFF04
56 #define TIOR0_ADDR 0x05FFFF05
57 #define TIER0_ADDR 0x05FFFF06
58 #define TSR0_ADDR 0x05FFFF07
59 #define TCNT0_ADDR 0x05FFFF08
60 #define GRA0_ADDR 0x05FFFF0A
61 #define GRB0_ADDR 0x05FFFF0C
62 #define TCR1_ADDR 0x05FFFF0E
63 #define TIOR1_ADDR 0x05FFFF0F
64 #define TIER1_ADDR 0x05FFFF10
65 #define TSR1_ADDR 0x05FFFF11
66 #define TCNT1_ADDR 0x05FFFF12
67 #define GRA1_ADDR 0x05FFFF14
68 #define GRB1_ADDR 0x05FFFF16
69 #define TCR2_ADDR 0x05FFFF18
70 #define TIOR2_ADDR 0x05FFFF19
71 #define TIER2_ADDR 0x05FFFF1A
72 #define TSR2_ADDR 0x05FFFF1B
73 #define TCNT2_ADDR 0x05FFFF1C
74 #define GRA2_ADDR 0x05FFFF1E
75 #define GRB2_ADDR 0x05FFFF20
76 #define TCR3_ADDR 0x05FFFF22
77 #define TIOR3_ADDR 0x05FFFF23
78 #define TIER3_ADDR 0x05FFFF24
79 #define TSR3_ADDR 0x05FFFF25
80 #define TCNT3_ADDR 0x05FFFF26
81 #define GRA3_ADDR 0x05FFFF28
82 #define GRB3_ADDR 0x05FFFF2A
83 #define BRA3_ADDR 0x05FFFF2C
84 #define BRB3_ADDR 0x05FFFF2E
85 #define TOCR_ADDR 0x05FFFF31
86 #define TCR4_ADDR 0x05FFFF32
87 #define TIOR4_ADDR 0x05FFFF33
88 #define TIER4_ADDR 0x05FFFF34
89 #define TSR4_ADDR 0x05FFFF35
90 #define TCNT4_ADDR 0x05FFFF36
91 #define GRA4_ADDR 0x05FFFF38
92 #define GRB4_ADDR 0x05FFFF3A
93 #define BRA4_ADDR 0x05FFFF3C
94 #define BRB4_ADDR 0x05FFFF3E
96 #define SAR0_ADDR 0x05FFFF40
97 #define DAR0_ADDR 0x05FFFF44
98 #define DMAOR_ADDR 0x05FFFF48
99 #define DTCR0_ADDR 0x05FFFF4A
100 #define CHCR0_ADDR 0x05FFFF4E
101 #define SAR1_ADDR 0x05FFFF50
102 #define DAR1_ADDR 0x05FFFF54
103 #define DTCR1_ADDR 0x05FFFF5A
104 #define CHCR1_ADDR 0x05FFFF5E
105 #define SAR2_ADDR 0x05FFFF60
106 #define DAR2_ADDR 0x05FFFF64
107 #define DTCR2_ADDR 0x05FFFF6A
108 #define CHCR2_ADDR 0x05FFFF6E
109 #define SAR3_ADDR 0x05FFFF70
110 #define DAR3_ADDR 0x05FFFF74
111 #define DTCR3_ADDR 0x05FFFF7A
112 #define CHCR3_ADDR 0x05FFFF7E
114 #define IPRA_ADDR 0x05FFFF84
115 #define IPRB_ADDR 0x05FFFF86
116 #define IPRC_ADDR 0x05FFFF88
117 #define IPRD_ADDR 0x05FFFF8A
118 #define IPRE_ADDR 0x05FFFF8C
119 #define ICR_ADDR 0x05FFFF8E
121 #define BARH_ADDR 0x05FFFF90
122 #define BARL_ADDR 0x05FFFF92
123 #define BAMRH_ADDR 0x05FFFF94
124 #define BAMRL_ADDR 0x05FFFF96
125 #define BBR_ADDR 0x05FFFF98
127 #define BCR_ADDR 0x05FFFFA0
128 #define WCR1_ADDR 0x05FFFFA2
129 #define WCR2_ADDR 0x05FFFFA4
130 #define WCR3_ADDR 0x05FFFFA6
131 #define DCR_ADDR 0x05FFFFA8
132 #define PCR_ADDR 0x05FFFFAA
133 #define RCR_ADDR 0x05FFFFAC
134 #define RTCSR_ADDR 0x05FFFFAE
135 #define RTCNT_ADDR 0x05FFFFB0
136 #define RTCOR_ADDR 0x05FFFFB2
138 #define TCSR_ADDR 0x05FFFFB8
139 #define TCNT_ADDR 0x05FFFFB9
140 #define RSTCSR_ADDR 0x05FFFFBB
142 #define SBYCR_ADDR 0x05FFFFBC
144 #define PADR_ADDR 0x05FFFFC0
145 #define PBDR_ADDR 0x05FFFFC2
146 #define PAIOR_ADDR 0x05FFFFC4
147 #define PBIOR_ADDR 0x05FFFFC6
148 #define PACR1_ADDR 0x05FFFFC8
149 #define PACR2_ADDR 0x05FFFFCA
150 #define PBCR1_ADDR 0x05FFFFCC
151 #define PBCR2_ADDR 0x05FFFFCE
152 #define PCDR_ADDR 0x05FFFFD0
154 #define CASCR_ADDR 0x05FFFFEE
156 /* byte halves of the ports */
157 #define PADRH_ADDR 0x05FFFFC0
158 #define PADRL_ADDR 0x05FFFFC1
159 #define PBDRH_ADDR 0x05FFFFC2
160 #define PBDRL_ADDR 0x05FFFFC3
161 #define PAIORH_ADDR 0x05FFFFC4
162 #define PAIORL_ADDR 0x05FFFFC5
163 #define PBIORH_ADDR 0x05FFFFC6
164 #define PBIORL_ADDR 0x05FFFFC7
167 /* A/D control/status register bits */
168 #define ADCSR_CH 0x07 /* Channel/group select */
169 #define ADCSR_CKS 0x08 /* Clock select */
170 #define ADCSR_SCAN 0x10 /* Scan mode */
171 #define ADCSR_ADST 0x20 /* A/D start */
172 #define ADCSR_ADIE 0x40 /* A/D interrupt enable */
173 #define ADCSR_ADF 0x80 /* A/D end flag */
175 /* A/D control register bits */
176 #define ADCR_TRGE 0x80 /* Trigger enable */
178 /* register macros for direct access: */
180 #define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
181 #define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
182 #define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
183 #define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
184 #define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
185 #define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
186 #define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
187 #define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
188 #define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
189 #define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
190 #define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
191 #define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
193 #define ADDRA (*((volatile unsigned short*)ADDRAH_ADDR)) /* combined */
194 #define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
195 #define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
196 #define ADDRB (*((volatile unsigned short*)ADDRBH_ADDR)) /* combined */
197 #define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
198 #define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
199 #define ADDRC (*((volatile unsigned short*)ADDRCH_ADDR)) /* combined */
200 #define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
201 #define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
202 #define ADDRD (*((volatile unsigned short*)ADDRDH_ADDR)) /* combined */
203 #define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
204 #define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
205 #define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
206 #define ADCR (*((volatile unsigned char*)ADCR_ADDR))
208 #define TSTR (*((volatile unsigned char*)TSTR_ADDR))
209 #define TSNC (*((volatile unsigned char*)TSNC_ADDR))
210 #define TMDR (*((volatile unsigned char*)TMDR_ADDR))
211 #define TFCR (*((volatile unsigned char*)TFCR_ADDR))
212 #define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
213 #define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
214 #define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
215 #define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
216 #define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
217 #define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
218 #define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
219 #define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
220 #define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
221 #define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
222 #define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
223 #define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
224 #define GRA1 (*((volatile unsigned short*)GRA1_ADDR))
225 #define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
226 #define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
227 #define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
228 #define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
229 #define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
230 #define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
231 #define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
232 #define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
233 #define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
234 #define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
235 #define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
236 #define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
237 #define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
238 #define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
239 #define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
240 #define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
241 #define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
242 #define TOCR (*((volatile unsigned char*)TOCR_ADDR))
243 #define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
244 #define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
245 #define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
246 #define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
247 #define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
248 #define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
249 #define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
250 #define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
251 #define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
253 #define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
254 #define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
255 #define DMAOR (*((volatile unsigned short*)DMAOR_ADDR))
256 #define DTCR0 (*((volatile unsigned short*)DTCR0_ADDR))
257 #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
258 #define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
259 #define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
260 #define DTCR1 (*((volatile unsigned short*)DTCR1_ADDR))
261 #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
262 #define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
263 #define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
264 #define DTCR2 (*((volatile unsigned short*)DTCR2_ADDR))
265 #define CHCR2 (*((volatile unsigned short*)CHCR2_ADDR))
266 #define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
267 #define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
268 #define DTCR3 (*((volatile unsigned short*)DTCR3_ADDR))
269 #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
271 #define IPRA (*((volatile unsigned short*)IPRA_ADDR))
272 #define IPRB (*((volatile unsigned short*)IPRB_ADDR))
273 #define IPRC (*((volatile unsigned short*)IPRC_ADDR))
274 #define IPRD (*((volatile unsigned short*)IPRD_ADDR))
275 #define IPRE (*((volatile unsigned short*)IPRE_ADDR))
276 #define ICR (*((volatile unsigned short*)ICR_ADDR))
278 #define BAR (*((volatile unsigned long*)BARH_ADDR)) /* combined */
279 #define BARH (*((volatile unsigned short*)BARH_ADDR))
280 #define BARL (*((volatile unsigned short*)BARL_ADDR))
281 #define BAMR (*((volatile unsigned long*)BAMRH_ADDR)) /* combined */
282 #define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
283 #define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
284 #define BBR (*((volatile unsigned short*)BBR_ADDR))
286 #define BCR (*((volatile unsigned short*)BCR_ADDR))
287 #define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
288 #define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
289 #define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
290 #define DCR (*((volatile unsigned short*)DCR_ADDR))
291 #define PCR (*((volatile unsigned short*)PCR_ADDR))
292 #define RCR (*((volatile unsigned short*)RCR_ADDR))
293 #define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
294 #define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
295 #define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
297 #define TCSR_R (*((volatile unsigned char*)TCSR_ADDR))
298 #define TCSR_W (*((volatile unsigned short*)(TCSR_ADDR & ~1)))
299 #define TCNT_R (*((volatile unsigned char*)TCNT_ADDR))
300 #define TCNT_W (*((volatile unsigned short*)(TCNT_ADDR & ~1)))
301 #define RSTCSR_R (*((volatile unsigned char*)RSTCSR_ADDR))
302 #define RSTCSR_W (*((volatile unsigned short*)(RSTCSR_ADDR & ~1)))
304 #define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
306 #define PADR (*((volatile unsigned short*)PADR_ADDR))
307 #define PBDR (*((volatile unsigned short*)PBDR_ADDR))
308 #define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
309 #define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
310 #define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
311 #define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
312 #define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
313 #define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
314 #define PCDR (*((volatile unsigned short*)PCDR_ADDR))
316 #define CASCR (*((volatile unsigned char*)CASCR_ADDR))
318 /* byte halves of the ports */
319 #define PADRH (*((volatile unsigned char*)PADRH_ADDR))
320 #define PADRL (*((volatile unsigned char*)PADRL_ADDR))
321 #define PBDRH (*((volatile unsigned char*)PBDRH_ADDR))
322 #define PBDRL (*((volatile unsigned char*)PBDRL_ADDR))
323 #define PAIORH (*((volatile unsigned char*)PAIORH_ADDR))
324 #define PAIORL (*((volatile unsigned char*)PAIORL_ADDR))
325 #define PBIORH (*((volatile unsigned char*)PBIORH_ADDR))
326 #define PBIORL (*((volatile unsigned char*)PBIORL_ADDR))
329 /***************************************************************************
330 * Register bit definitions
331 **************************************************************************/
334 * Serial mode register bits
337 #define SYNC_MODE 0x80
338 #define SEVEN_BIT_DATA 0x40
339 #define PARITY_ON 0x20
340 #define ODD_PARITY 0x10
341 #define STOP_BITS_2 0x08
342 #define ENABLE_MULTIP 0x04
343 #define PHI_64 0x03
344 #define PHI_16 0x02
345 #define PHI_4 0x01
348 * Serial control register bits
350 #define SCI_TIE 0x80 /* Transmit interrupt enable */
351 #define SCI_RIE 0x40 /* Receive interrupt enable */
352 #define SCI_TE 0x20 /* Transmit enable */
353 #define SCI_RE 0x10 /* Receive enable */
354 #define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
355 #define SCI_TEIE 0x04 /* Transmit end interrupt enable */
356 #define SCI_CKE1 0x02 /* Clock enable 1 */
357 #define SCI_CKE0 0x01 /* Clock enable 0 */
360 * Serial status register bits
362 #define SCI_TDRE 0x80 /* Transmit data register empty */
363 #define SCI_RDRF 0x40 /* Receive data register full */
364 #define SCI_ORER 0x20 /* Overrun error */
365 #define SCI_FER 0x10 /* Framing error */
366 #define SCI_PER 0x08 /* Parity error */
367 #define SCI_TEND 0x04 /* Transmit end */
368 #define SCI_MPB 0x02 /* Multiprocessor bit */
369 #define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
371 #endif