firmware/export/pnx0101.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Tomasz Malesinski
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #ifndef __PNX0101_H__
  21 #define __PNX0101_H__
  22
  23 #define GPIO0_READ (*(volatile unsigned long *)0x80003000)
  24 #define GPIO0_SET  (*(volatile unsigned long *)0x80003014)
  25 #define GPIO0_CLR  (*(volatile unsigned long *)0x80003018)
  26 #define GPIO1_READ (*(volatile unsigned long *)0x80003040)
  27 #define GPIO1_SET  (*(volatile unsigned long *)0x80003054)
  28 #define GPIO1_CLR  (*(volatile unsigned long *)0x80003058)
  29 #define GPIO2_READ (*(volatile unsigned long *)0x80003080)
  30 #define GPIO2_SET  (*(volatile unsigned long *)0x80003094)
  31 #define GPIO2_CLR  (*(volatile unsigned long *)0x80003098)
  32 #define GPIO3_READ (*(volatile unsigned long *)0x800030c0)
  33 #define GPIO3_SET  (*(volatile unsigned long *)0x800030d4)
  34 #define GPIO3_CLR  (*(volatile unsigned long *)0x800030d8)
  35 #define GPIO4_READ (*(volatile unsigned long *)0x80003100)
  36 #define GPIO4_SET  (*(volatile unsigned long *)0x80003114)
  37 #define GPIO4_CLR  (*(volatile unsigned long *)0x80003118)
  38 #define GPIO5_READ (*(volatile unsigned long *)0x80003140)
  39 #define GPIO5_SET  (*(volatile unsigned long *)0x80003154)
  40 #define GPIO5_CLR  (*(volatile unsigned long *)0x80003158)
  41 #define GPIO6_READ (*(volatile unsigned long *)0x80003180)
  42 #define GPIO6_SET  (*(volatile unsigned long *)0x80003194)
  43 #define GPIO6_CLR  (*(volatile unsigned long *)0x80003198)
  44 #define GPIO7_READ (*(volatile unsigned long *)0x800031c0)
  45 #define GPIO7_SET  (*(volatile unsigned long *)0x800031d4)
  46 #define GPIO7_CLR  (*(volatile unsigned long *)0x800031d8)
  47
  48 #define LCDREG04 (*(volatile unsigned long *)0x80104004)
  49 #define LCDSTAT  (*(volatile unsigned long *)0x80104008)
  50 #define LCDREG10 (*(volatile unsigned long *)0x80104010)
  51 #define LCDCMD   (*(volatile unsigned long *)0x80104020)
  52 #define LCDDATA  (*(volatile unsigned long *)0x80104030)
  53
  54 #define TIMERR00 (*(volatile unsigned long *)0x80020000)
  55 #define TIMERR08 (*(volatile unsigned long *)0x80020008)
  56 #define TIMERR0C (*(volatile unsigned long *)0x8002000c)
  57
  58 #define ADCCH0   (*(volatile unsigned long *)0x80002400)
  59 #define ADCCH1   (*(volatile unsigned long *)0x80002404)
  60 #define ADCCH2   (*(volatile unsigned long *)0x80002408)
  61 #define ADCCH3   (*(volatile unsigned long *)0x8000240c)
  62 #define ADCCH4   (*(volatile unsigned long *)0x80002410)
  63 #define ADCST    (*(volatile unsigned long *)0x80002420)
  64 #define ADCR24   (*(volatile unsigned long *)0x80002424)
  65 #define ADCR28   (*(volatile unsigned long *)0x80002428)
  66
  67 #define DMAINTSTAT   (*(volatile unsigned long *)0x80104c04)
  68 #define DMAINTEN     (*(volatile unsigned long *)0x80104c08)
  69
  70 #define DMASRC(n)    (*(volatile unsigned long *)(0x80104800 + (n) * 0x20))
  71 #define DMADEST(n)   (*(volatile unsigned long *)(0x80104804 + (n) * 0x20))
  72 #define DMALEN(n)    (*(volatile unsigned long *)(0x80104808 + (n) * 0x20))
  73 #define DMAR0C(n)    (*(volatile unsigned long *)(0x8010480c + (n) * 0x20))
  74 #define DMAR10(n)    (*(volatile unsigned long *)(0x80104810 + (n) * 0x20))
  75 #define DMAR1C(n)    (*(volatile unsigned long *)(0x8010481c + (n) * 0x20))
  76
  77 #define MMUBLOCK(n)  (*(volatile unsigned long *)(0x80105018 + (n) * 4))
  78
  79 #define CODECVOL     (*(volatile unsigned long *)0x80200398)
  80
  81 #ifndef ASM
  82
  83 /* Clock generation unit */
  84
  85 struct pnx0101_cgu {
  86     unsigned long base_scr[12];
  87     unsigned long base_fs1[12];
  88     unsigned long base_fs2[12];
  89     unsigned long base_ssr[12];
  90     unsigned long clk_pcr[73];
  91     unsigned long clk_psr[73];
  92     unsigned long clk_esr[67];
  93     unsigned long base_bcr[3];
  94     unsigned long base_fdc[18];
  95 };
  96
  97 #define CGU (*(volatile struct pnx0101_cgu *)0x80004000)
  98
  99 #define PNX0101_SEL_STAGE_SYS  0
 100 #define PNX0101_SEL_STAGE_APB0 1
 101 #define PNX0101_SEL_STAGE_APB1 2
 102 #define PNX0101_SEL_STAGE_APB3 3
 103 #define PNX0101_SEL_STAGE_DAIO 9
 104
 105 #define PNX0101_HIPREC_FDC 16
 106
 107 #define PNX0101_FIRST_DIV_SYS  0
 108 #define PNX0101_N_DIV_SYS      7
 109 #define PNX0101_FIRST_DIV_APB0 7
 110 #define PNX0101_N_DIV_APB0     2
 111 #define PNX0101_FIRST_DIV_APB1 9
 112 #define PNX0101_N_DIV_APB1     1
 113 #define PNX0101_FIRST_DIV_APB3 10
 114 #define PNX0101_N_DIV_APB3     1
 115 #define PNX0101_FIRST_DIV_DAIO 12
 116 #define PNX0101_N_DIV_DAIO     6
 117
 118 #define PNX0101_BCR_SYS  0
 119 #define PNX0101_BCR_APB0 1
 120 #define PNX0101_BCR_DAIO 2
 121
 122 #define PNX0101_FIRST_ESR_SYS  0
 123 #define PNX0101_N_ESR_SYS      28
 124 #define PNX0101_FIRST_ESR_APB0 28
 125 #define PNX0101_N_ESR_APB0     9
 126 #define PNX0101_FIRST_ESR_APB1 37
 127 #define PNX0101_N_ESR_APB1     4
 128 #define PNX0101_FIRST_ESR_APB3 41
 129 #define PNX0101_N_ESR_APB3     16
 130 #define PNX0101_FIRST_ESR_DAIO 58
 131 #define PNX0101_N_ESR_DAIO     9
 132
 133 #define PNX0101_ESR_APB1 0x25
 134 #define PNX0101_ESR_T0   0x26
 135 #define PNX0101_ESR_T1   0x27
 136 #define PNX0101_ESR_I2C  0x28
 137
 138 #define PNX0101_CLOCK_APB1 0x25
 139 #define PNX0101_CLOCK_T0   0x26
 140 #define PNX0101_CLOCK_T1   0x27
 141 #define PNX0101_CLOCK_I2C  0x28
 142
 143 #define PNX0101_MAIN_CLOCK_FAST     1
 144 #define PNX0101_MAIN_CLOCK_MAIN_PLL 9
 145
 146 struct pnx0101_pll {
 147     unsigned long hpfin;
 148     unsigned long hpmdec;
 149     unsigned long hpndec;
 150     unsigned long hppdec;
 151     unsigned long hpmode;
 152     unsigned long hpstat;
 153     unsigned long hpack;
 154     unsigned long hpreq;
 155     unsigned long hppad1;
 156     unsigned long hppad2;
 157     unsigned long hppad3;
 158     unsigned long hpselr;
 159     unsigned long hpseli;
 160     unsigned long hpselp;
 161     unsigned long lpfin;
 162     unsigned long lppdn;
 163     unsigned long lpmbyp;
 164     unsigned long lplock;
 165     unsigned long lpdbyp;
 166     unsigned long lpmsel;
 167     unsigned long lppsel;
 168 };
 169
 170 #define PLL (*(volatile struct pnx0101_pll *)0x80004cac)
 171
 172 struct pnx0101_emc {
 173     unsigned long control;
 174     unsigned long status;
 175 };
 176
 177 #define EMC (*(volatile struct pnx0101_emc *)0x80008000)
 178
 179 struct pnx0101_emcstatic {
 180     unsigned long config;
 181     unsigned long waitwen;
 182     unsigned long waitoen;
 183     unsigned long waitrd;
 184     unsigned long waitpage;
 185     unsigned long waitwr;
 186     unsigned long waitturn;
 187 };
 188
 189 #define EMCSTATIC0 (*(volatile struct pnx0101_emcstatic *)0x80008200)
 190 #define EMCSTATIC1 (*(volatile struct pnx0101_emcstatic *)0x80008220)
 191 #define EMCSTATIC2 (*(volatile struct pnx0101_emcstatic *)0x80008240)
 192
 193 /* Timers */
 194
 195 struct pnx0101_timer {
 196     unsigned long load;
 197     unsigned long value;
 198     unsigned long ctrl;
 199     unsigned long clr;
 200 };
 201
 202 #define TIMER0 (*(volatile struct pnx0101_timer *)0x80020000)
 203 #define TIMER1 (*(volatile struct pnx0101_timer *)0x80020400)
 204
 205 /* Interrupt controller */
 206
 207 #define IRQ_TIMER0 5
 208 #define IRQ_TIMER1 6
 209 #define IRQ_DMA    28
 210
 211 #define INTPRIOMASK ((volatile unsigned long *)0x80300000)
 212 #define INTVECTOR   ((volatile unsigned long *)0x80300100)
 213 #define INTPENDING  (*(volatile unsigned long *)0x80300200)
 214 #define INTFEATURES (*(volatile unsigned long *)0x80300300)
 215 #define INTREQ      ((volatile unsigned long *)0x80300400)
 216
 217 #define INTREQ_WEPRIO   0x10000000
 218 #define INTREQ_WETARGET 0x08000000
 219 #define INTREQ_WEENABLE 0x04000000
 220 #define INTREQ_WEACTVLO 0x02000000
 221 #define INTREQ_ENABLE   0x00010000
 222
 223 /* General purpose DMA */
 224
 225 struct pnx0101_dma_channel {
 226     unsigned long source;
 227     unsigned long dest;
 228     unsigned long length;
 229     unsigned long config;
 230     unsigned long enable;
 231     unsigned long pad1;
 232     unsigned long pad2;
 233     unsigned long count;
 234 };
 235
 236 #define DMACHANNEL ((volatile struct pnx0101_dma_channel *)0x80104800)
 237
 238 struct pnx0101_dma {
 239     unsigned long enable;
 240     unsigned long stat;
 241     unsigned long irqmask;
 242     unsigned long softint;
 243 };
 244
 245 #define DMA (*(volatile struct pnx0101_dma *)0x80104c00)
 246
 247 struct pnx0101_audio {
 248     unsigned long pad1;
 249     unsigned long siocr;
 250     unsigned long pad2;
 251     unsigned long pad3;
 252     unsigned long pad4;
 253     unsigned long pad5;
 254     unsigned long ddacctrl;
 255     unsigned long ddacstat;
 256     unsigned long ddacset;
 257 };
 258
 259 #define AUDIO (*(volatile struct pnx0101_audio *)0x80200380)
 260
 261 #endif /* ASM */
 262
 263 #endif