1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2002 by Linus Nielsen Feltzing
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
18 ****************************************************************************/
27 #if CONFIG_CPU == SH7034
28 /**************************************************************************
29 ** The A/D conversion is done every tick, in three steps:
31 ** 1) On the tick interrupt, the conversion of channels 0-3 is started, and
32 ** the A/D interrupt is enabled.
34 ** 2) After the conversion is done (approx. 256*4 cycles later), an interrupt
35 ** is generated at level 1, which is the same level as the tick interrupt
36 ** itself. This interrupt will be pending until the tick interrupt is
38 ** When the A/D interrupt is finally served, it will read the results
39 ** from the first conversion and start the conversion of channels 4-7.
41 ** 3) When the conversion of channels 4-7 is finished, the interrupt is
42 ** triggered again, and the results are read. This time, no new
43 ** conversion is started, it will be done in the next tick interrupt.
45 ** Thus, each channel will be updated HZ times per second.
47 *************************************************************************/
49 static int current_channel
;
50 static unsigned short adcdata
[NUM_ADC_CHANNELS
];
52 static void adc_tick(void)
54 /* Start a conversion of channel group 0. This will trigger an interrupt,
55 and the interrupt handler will take care of group 1. */
58 ADCSR
= ADCSR_ADST
| ADCSR_ADIE
| ADCSR_SCAN
| 3;
68 if(current_channel
== 0)
70 adcdata
[0] = ADDRA
>> 6;
71 adcdata
[1] = ADDRB
>> 6;
72 adcdata
[2] = ADDRC
>> 6;
73 adcdata
[3] = ADDRD
>> 6;
76 /* Convert the next group */
77 ADCSR
= ADCSR_ADST
| ADCSR_ADIE
| ADCSR_SCAN
| 7;
81 adcdata
[4] = ADDRA
>> 6;
82 adcdata
[5] = ADDRB
>> 6;
83 adcdata
[6] = ADDRC
>> 6;
84 adcdata
[7] = ADDRD
>> 6;
89 unsigned short adc_read(int channel
)
91 return adcdata
[channel
];
96 ADCR
= 0x7f; /* No external trigger; other bits should be 1 according
103 /* Enable the A/D IRQ on level 1 */
104 IPRE
= (IPRE
& 0xf0ff) | 0x0100;
106 tick_add_task(adc_tick
);
108 sleep(2); /* Ensure valid readings when adc_init returns */
110 #elif CONFIG_CPU == MCF5249
111 static unsigned char adcdata
[NUM_ADC_CHANNELS
];
113 #ifdef IRIVER_H300_SERIES
114 static int channelnum
[] =
121 unsigned char adc_scan(int channel
)
125 pcf50606_write(0x2f, 0x80 | (channelnum
[channel
] << 1) | 1);
126 data
= pcf50606_read(0x30);
128 adcdata
[channel
] = data
;
134 #define CS_LO and_l(~0x80, &GPIO_OUT)
135 #define CS_HI or_l(0x80, &GPIO_OUT)
136 #define CLK_LO and_l(~0x00400000, &GPIO_OUT)
137 #define CLK_HI or_l(0x00400000, &GPIO_OUT)
138 #define DO (GPIO_READ & 0x80000000)
139 #define DI_LO and_l(~0x00200000, &GPIO_OUT)
140 #define DI_HI or_l(0x00200000, &GPIO_OUT)
143 #define DELAY do { int _x; for(_x=0;_x<10;_x++);} while (0)
145 unsigned char adc_scan(int channel
)
147 unsigned char data
= 0;
152 DI_HI
; /* Start bit */
158 DI_HI
; /* Single channel */
164 if(channel
& 1) /* LSB of channel number */
173 if(channel
& 2) /* MSB of channel number */
184 for(i
= 0;i
< 8;i
++) /* 8 bits of data */
196 adcdata
[channel
] = data
;
202 unsigned short adc_read(int channel
)
204 return adcdata
[channel
];
207 static int adc_counter
;
209 static void adc_tick(void)
211 if(++adc_counter
== HZ
)
214 adc_scan(ADC_BATTERY
);
220 #ifdef IRIVER_H300_SERIES
222 or_l(0x80600080, &GPIO_FUNCTION
); /* GPIO7: CS
223 GPIO21: Data In (to the ADC)
225 GPIO31: Data Out (from the ADC) */
226 or_l(0x00600080, &GPIO_ENABLE
);
227 or_l(0x80, &GPIO_OUT
); /* CS high */
228 and_l(~0x00400000, &GPIO_OUT
); /* CLK low */
231 adc_scan(ADC_BATTERY
);
233 tick_add_task(adc_tick
);
236 #elif CONFIG_CPU == TCC730
239 /**************************************************************************
241 ** Each channel will be updated HZ/CHANNEL_ORDER_SIZE times per second.
243 *************************************************************************/
245 static int current_channel
;
246 static int current_channel_idx
;
247 static unsigned short adcdata
[NUM_ADC_CHANNELS
];
249 #define CHANNEL_ORDER_SIZE 2
250 static int channel_order
[CHANNEL_ORDER_SIZE
] = {6,7};
252 static void adc_tick(void)
254 if (ADCON
& (1 << 3)) {
255 /* previous conversion finished? */
256 adcdata
[current_channel
] = ADDATA
>> 6;
257 if (++current_channel_idx
>= CHANNEL_ORDER_SIZE
)
258 current_channel_idx
= 0;
259 current_channel
= channel_order
[current_channel_idx
];
260 int adcon
= (current_channel
<< 4) | 1;
265 unsigned short adc_read(int channel
)
267 return adcdata
[channel
];
272 current_channel_idx
= 0;
273 current_channel
= channel_order
[current_channel_idx
];
275 ADCON
= (current_channel
<< 4) | 1;
277 tick_add_task(adc_tick
);
279 sleep(2); /* Ensure valid readings when adc_init returns */
282 #elif CONFIG_CPU == PP5020
284 /* TODO: Implement adc.c */
286 unsigned short adc_read(int channel
)
297 #elif CONFIG_CPU == PNX0101
299 static unsigned short adcdata
[NUM_ADC_CHANNELS
];
301 unsigned short adc_read(int channel
)
303 return adcdata
[channel
];
306 static void adc_tick(void)
309 adcdata
[0] = ADCCH0
& 0x3ff;
310 adcdata
[1] = ADCCH1
& 0x3ff;
311 adcdata
[2] = ADCCH2
& 0x3ff;
312 adcdata
[3] = ADCCH3
& 0x3ff;
313 adcdata
[4] = ADCCH4
& 0x3ff;
325 while (!(ADCST
& 0x10));
328 tick_add_task(adc_tick
);