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Fix typo.
[Rockbox.git] / firmware / export / arcotg_udc.h
blobe016321b37a0c417a24c3fe0b2f43e6aa3e6ca23
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Barry Wardell
11 *
12 * ARC OTG USB device driver based on code from the Linux Target Image Builder
13 * from Freescale - http://www.bitshrine.org/ and
14 * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
15 * Adapted for Rockbox in January 2007
16 * Original file: drivers/usb/gadget/arcotg_udc.h
17 *
18 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
19 *
20 * Based on mpc-udc.h
21 * Author: Li Yang (leoli@freescale.com)
22 * Jiang Bo (Tanya.jiang@freescale.com)
23 *
24 * All files in this archive are subject to the GNU General Public License.
25 * See the file COPYING in the source tree root for full license agreement.
26 *
27 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
28 * KIND, either express or implied.
29 *
30 ****************************************************************************/
31
32 /*
33 * Freescale USB device/endpoint management registers
34 */
35 #ifndef __ARCOTG_UDC_H
36 #define __ARCOTG_UDC_H
37
38 #include "cpu.h"
39
40 #define USB_MAX_ENDPOINTS 8
41 #define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2)
42 #define USB_MAX_CTRL_PAYLOAD 64
43
44 /* USB DR device mode registers (Little Endian) */
45 /* Identification registers */
46 #define UDC_ID (*(volatile unsigned int *)(USB_BASE+0x000))
47 #define UDC_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
48 #define UDC_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
49 #define UDC_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
50 #define UDC_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
51
52 /* Capability registers */
53 #define UDC_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100)) /* Capability Register Length */
54 #define UDC_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102)) /* Host Controller Interface Version */
55 #define UDC_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104)) /* Host Controller Structual Parameters */
56 #define UDC_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108)) /* Host Controller Capability Parameters */
57 #define UDC_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120)) /* Device Controller Interface Version */
58 #define UDC_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124)) /* Device Controller Capability Parameters */
59
60 /* Operation registers */
61 #define UDC_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) /* USB Command Register */
62 #define UDC_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144)) /* USB Status Register */
63 #define UDC_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148)) /* USB Interrupt Enable Register */
64 #define UDC_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c)) /* Frame Index Register */
65 #define UDC_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154)) /* Device Address */
66 #define UDC_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) /* Endpoint List Address Register */
67 #define UDC_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160)) /* Master Interface Data Burst Size Register */
68 #define UDC_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164)) /* Transmit FIFO Tuning Controls Register */
69 #define UDC_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170))
70 #define UDC_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180)) /* Configure Flag Register */
71 #define UDC_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) /* Port 1 Status and Control Register */
72 #define UDC_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4)) /* On-The-Go Status and Control */
73 #define UDC_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) /* USB Mode Register */
74 #define UDC_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) /* Endpoint Setup Status Register */
75 #define UDC_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) /* Endpoint Initialization Register */
76 #define UDC_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4)) /* Endpoint Flush Register */
77 #define UDC_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8)) /* Endpoint Status Register */
78 #define UDC_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) /* Endpoint Complete Register */
79 #define UDC_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) /* Endpoint 0 Control Register */
80 #define UDC_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) /* Endpoint 1 Control Register */
81 #define UDC_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) /* Endpoint 2 Control Register */
82 #define UDC_ENDPTCTRL3 (*(volatile unsigned int *)(USB_BASE+0x1cc)) /* Endpoint 3 Control Register */
83 #define UDC_ENDPTCTRL4 (*(volatile unsigned int *)(USB_BASE+0x1d0)) /* Endpoint 4 Control Register */
84 #define UDC_ENDPTCTRL5 (*(volatile unsigned int *)(USB_BASE+0x1d4)) /* Endpoint 5 Control Register */
85 #define UDC_ENDPTCTRL6 (*(volatile unsigned int *)(USB_BASE+0x1d8)) /* Endpoint 6 Control Register */
86 #define UDC_ENDPTCTRL7 (*(volatile unsigned int *)(USB_BASE+0x1dc)) /* Endpoint 7 Control Register */
87 #define UDC_ENDPTCTRL(x) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(x))) /* Endpoint X Control Register */
88
89 /* ep0 transfer state */
90 #define WAIT_FOR_SETUP 0
91 #define DATA_STATE_XMIT 1
92 #define DATA_STATE_NEED_ZLP 2
93 #define WAIT_FOR_OUT_STATUS 3
94 #define DATA_STATE_RECV 4
95
96 /* Frame Index Register Bit Masks */
97 #define USB_FRINDEX_MASKS (0x3fff)
98
99 /* USB CMD Register Bit Masks */
100 #define USB_CMD_RUN (0x00000001)
101 #define USB_CMD_CTRL_RESET (0x00000002)
102 #define USB_CMD_PERIODIC_SCHEDULE_EN (0x00000010)
103 #define USB_CMD_ASYNC_SCHEDULE_EN (0x00000020)
104 #define USB_CMD_INT_AA_DOORBELL (0x00000040)
105 #define USB_CMD_ASP (0x00000300)
106 #define USB_CMD_ASYNC_SCH_PARK_EN (0x00000800)
107 #define USB_CMD_SUTW (0x00002000)
108 #define USB_CMD_ATDTW (0x00004000)
109 #define USB_CMD_ITC (0x00FF0000)
110
111 /* bit 15,3,2 are frame list size */
112 #define USB_CMD_FRAME_SIZE_1024 (0x00000000)
113 #define USB_CMD_FRAME_SIZE_512 (0x00000004)
114 #define USB_CMD_FRAME_SIZE_256 (0x00000008)
115 #define USB_CMD_FRAME_SIZE_128 (0x0000000C)
116 #define USB_CMD_FRAME_SIZE_64 (0x00008000)
117 #define USB_CMD_FRAME_SIZE_32 (0x00008004)
118 #define USB_CMD_FRAME_SIZE_16 (0x00008008)
119 #define USB_CMD_FRAME_SIZE_8 (0x0000800C)
120
121 /* bit 9-8 are async schedule park mode count */
122 #define USB_CMD_ASP_00 (0x00000000)
123 #define USB_CMD_ASP_01 (0x00000100)
124 #define USB_CMD_ASP_10 (0x00000200)
125 #define USB_CMD_ASP_11 (0x00000300)
126 #define USB_CMD_ASP_BIT_POS (8)
127
128 /* bit 23-16 are interrupt threshold control */
129 #define USB_CMD_ITC_NO_THRESHOLD (0x00000000)
130 #define USB_CMD_ITC_1_MICRO_FRM (0x00010000)
131 #define USB_CMD_ITC_2_MICRO_FRM (0x00020000)
132 #define USB_CMD_ITC_4_MICRO_FRM (0x00040000)
133 #define USB_CMD_ITC_8_MICRO_FRM (0x00080000)
134 #define USB_CMD_ITC_16_MICRO_FRM (0x00100000)
135 #define USB_CMD_ITC_32_MICRO_FRM (0x00200000)
136 #define USB_CMD_ITC_64_MICRO_FRM (0x00400000)
137 #define USB_CMD_ITC_BIT_POS (16)
138
139 /* USB STS Register Bit Masks */
140 #define USB_STS_INT (0x00000001)
141 #define USB_STS_ERR (0x00000002)
142 #define USB_STS_PORT_CHANGE (0x00000004)
143 #define USB_STS_FRM_LST_ROLL (0x00000008)
144 #define USB_STS_SYS_ERR (0x00000010)
145 #define USB_STS_IAA (0x00000020)
146 #define USB_STS_RESET (0x00000040)
147 #define USB_STS_SOF (0x00000080)
148 #define USB_STS_SUSPEND (0x00000100)
149 #define USB_STS_HC_HALTED (0x00001000)
150 #define USB_STS_RCL (0x00002000)
151 #define USB_STS_PERIODIC_SCHEDULE (0x00004000)
152 #define USB_STS_ASYNC_SCHEDULE (0x00008000)
153
154 /* USB INTR Register Bit Masks */
155 #define USB_INTR_INT_EN (0x00000001)
156 #define USB_INTR_ERR_INT_EN (0x00000002)
157 #define USB_INTR_PTC_DETECT_EN (0x00000004)
158 #define USB_INTR_FRM_LST_ROLL_EN (0x00000008)
159 #define USB_INTR_SYS_ERR_EN (0x00000010)
160 #define USB_INTR_ASYN_ADV_EN (0x00000020)
161 #define USB_INTR_RESET_EN (0x00000040)
162 #define USB_INTR_SOF_EN (0x00000080)
163 #define USB_INTR_DEVICE_SUSPEND (0x00000100)
164
165 /* Device Address bit masks */
166 #define USB_DEVICE_ADDRESS_MASK (0xFE000000)
167 #define USB_DEVICE_ADDRESS_BIT_POS (25)
168
169 /* endpoint list address bit masks */
170 #define USB_EP_LIST_ADDRESS_MASK (0xfffff800)
171
172 /* PORTSCX Register Bit Masks */
173 #define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001)
174 #define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002)
175 #define PORTSCX_PORT_ENABLE (0x00000004)
176 #define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008)
177 #define PORTSCX_OVER_CURRENT_ACT (0x00000010)
178 #define PORTSCX_OVER_CURRENT_CHG (0x00000020)
179 #define PORTSCX_PORT_FORCE_RESUME (0x00000040)
180 #define PORTSCX_PORT_SUSPEND (0x00000080)
181 #define PORTSCX_PORT_RESET (0x00000100)
182 #define PORTSCX_LINE_STATUS_BITS (0x00000C00)
183 #define PORTSCX_PORT_POWER (0x00001000)
184 #define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000)
185 #define PORTSCX_PORT_TEST_CTRL (0x000F0000)
186 #define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000)
187 #define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000)
188 #define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000)
189 #define PORTSCX_PHY_LOW_POWER_SPD (0x00800000)
190 #define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000)
191 #define PORTSCX_PORT_SPEED_MASK (0x0C000000)
192 #define PORTSCX_PORT_WIDTH (0x10000000)
193 #define PORTSCX_PHY_TYPE_SEL (0xC0000000)
194
195 /* bit 11-10 are line status */
196 #define PORTSCX_LINE_STATUS_SE0 (0x00000000)
197 #define PORTSCX_LINE_STATUS_JSTATE (0x00000400)
198 #define PORTSCX_LINE_STATUS_KSTATE (0x00000800)
199 #define PORTSCX_LINE_STATUS_UNDEF (0x00000C00)
200 #define PORTSCX_LINE_STATUS_BIT_POS (10)
201
202 /* bit 15-14 are port indicator control */
203 #define PORTSCX_PIC_OFF (0x00000000)
204 #define PORTSCX_PIC_AMBER (0x00004000)
205 #define PORTSCX_PIC_GREEN (0x00008000)
206 #define PORTSCX_PIC_UNDEF (0x0000C000)
207 #define PORTSCX_PIC_BIT_POS (14)
208
209 /* bit 19-16 are port test control */
210 #define PORTSCX_PTC_DISABLE (0x00000000)
211 #define PORTSCX_PTC_JSTATE (0x00010000)
212 #define PORTSCX_PTC_KSTATE (0x00020000)
213 #define PORTSCX_PTC_SEQNAK (0x00030000)
214 #define PORTSCX_PTC_PACKET (0x00040000)
215 #define PORTSCX_PTC_FORCE_EN (0x00050000)
216 #define PORTSCX_PTC_BIT_POS (16)
217
218 /* bit 27-26 are port speed */
219 #define PORTSCX_PORT_SPEED_FULL (0x00000000)
220 #define PORTSCX_PORT_SPEED_LOW (0x04000000)
221 #define PORTSCX_PORT_SPEED_HIGH (0x08000000)
222 #define PORTSCX_PORT_SPEED_UNDEF (0x0C000000)
223 #define PORTSCX_SPEED_BIT_POS (26)
224
225 /* bit 28 is parallel transceiver width for UTMI interface */
226 #define PORTSCX_PTW (0x10000000)
227 #define PORTSCX_PTW_8BIT (0x00000000)
228 #define PORTSCX_PTW_16BIT (0x10000000)
229
230 /* bit 31-30 are port transceiver select */
231 #define PORTSCX_PTS_UTMI (0x00000000)
232 #define PORTSCX_PTS_ULPI (0x80000000)
233 #define PORTSCX_PTS_FSLS (0xC0000000)
234 #define PORTSCX_PTS_BIT_POS (30)
235
236 /* USB MODE Register Bit Masks */
237 #define USB_MODE_CTRL_MODE_IDLE (0x00000000)
238 #define USB_MODE_CTRL_MODE_DEVICE (0x00000002)
239 #define USB_MODE_CTRL_MODE_HOST (0x00000003)
240 #define USB_MODE_CTRL_MODE_RSV (0x00000001)
241 #define USB_MODE_SETUP_LOCK_OFF (0x00000008)
242 #define USB_MODE_STREAM_DISABLE (0x00000010)
243
244 /* Endpoint Flush Register */
245 #define EPFLUSH_TX_OFFSET (0x00010000)
246 #define EPFLUSH_RX_OFFSET (0x00000000)
247
248 /* Endpoint Setup Status bit masks */
249 #define EP_SETUP_STATUS_MASK (0x0000003F)
250 #define EP_SETUP_STATUS_EP0 (0x00000001)
251
252 /* ENDPOINTCTRLx Register Bit Masks */
253 #define EPCTRL_TX_ENABLE (0x00800000)
254 #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */
255 #define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */
256 #define EPCTRL_TX_TYPE (0x000C0000)
257 #define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */
258 #define EPCTRL_TX_EP_STALL (0x00010000)
259 #define EPCTRL_RX_ENABLE (0x00000080)
260 #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */
261 #define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */
262 #define EPCTRL_RX_TYPE (0x0000000C)
263 #define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */
264 #define EPCTRL_RX_EP_STALL (0x00000001)
265
266 /* bit 19-18 and 3-2 are endpoint type */
267 #define EPCTRL_EP_TYPE_CONTROL (0)
268 #define EPCTRL_EP_TYPE_ISO (1)
269 #define EPCTRL_EP_TYPE_BULK (2)
270 #define EPCTRL_EP_TYPE_INTERRUPT (3)
271 #define EPCTRL_TX_EP_TYPE_SHIFT (18)
272 #define EPCTRL_RX_EP_TYPE_SHIFT (2)
273
274 /* SNOOPn Register Bit Masks */
275 #define SNOOP_ADDRESS_MASK (0xFFFFF000)
276 #define SNOOP_SIZE_ZERO (0x00) /* snooping disable */
277 #define SNOOP_SIZE_4KB (0x0B) /* 4KB snoop size */
278 #define SNOOP_SIZE_8KB (0x0C)
279 #define SNOOP_SIZE_16KB (0x0D)
280 #define SNOOP_SIZE_32KB (0x0E)
281 #define SNOOP_SIZE_64KB (0x0F)
282 #define SNOOP_SIZE_128KB (0x10)
283 #define SNOOP_SIZE_256KB (0x11)
284 #define SNOOP_SIZE_512KB (0x12)
285 #define SNOOP_SIZE_1MB (0x13)
286 #define SNOOP_SIZE_2MB (0x14)
287 #define SNOOP_SIZE_4MB (0x15)
288 #define SNOOP_SIZE_8MB (0x16)
289 #define SNOOP_SIZE_16MB (0x17)
290 #define SNOOP_SIZE_32MB (0x18)
291 #define SNOOP_SIZE_64MB (0x19)
292 #define SNOOP_SIZE_128MB (0x1A)
293 #define SNOOP_SIZE_256MB (0x1B)
294 #define SNOOP_SIZE_512MB (0x1C)
295 #define SNOOP_SIZE_1GB (0x1D)
296 #define SNOOP_SIZE_2GB (0x1E) /* 2GB snoop size */
297
298 /* pri_ctrl Register Bit Masks */
299 #define PRI_CTRL_PRI_LVL1 (0x0000000C)
300 #define PRI_CTRL_PRI_LVL0 (0x00000003)
301
302 /* si_ctrl Register Bit Masks */
303 #define SI_CTRL_ERR_DISABLE (0x00000010)
304 #define SI_CTRL_IDRC_DISABLE (0x00000008)
305 #define SI_CTRL_RD_SAFE_EN (0x00000004)
306 #define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002)
307 #define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001)
308
309 /* control Register Bit Masks */
310 #define USB_CTRL_IOENB (0x00000004)
311 #define USB_CTRL_ULPI_INT0EN (0x00000001)
312
313 /* Externally used functions */
314 int dr_controller_setup(void);
315 void dr_controller_run(void);
316 void dr_controller_stop(void);
317
318 #endif /* __ARCOTG_UDC_H */
Open Source Jukebox Firmware