firmware/export/i2c-coldfire.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 /*
  21  *  Driver for MCF52xx's I2C interface
  22  *  2005-02-17 hubble@mochine.com
  23  *
  24  */
  25
  26 #ifndef _I2C_COLDFIRE_H
  27 #define _I2C_COLDFIRE_H
  28
  29 #include "cpu.h"
  30
  31 void i2c_init(void);
  32 int i2c_read (volatile unsigned char *iface, unsigned char addr,
  33               unsigned char *buf, int count);
  34 int i2c_write(volatile unsigned char *iface, unsigned char addr,
  35               const unsigned char *buf, int count);
  36 void i2c_close(void);
  37 void i2c_adjust_prescale(int multiplier);
  38
  39 #define I2C_IFACE_0  ((volatile unsigned char *)&MADR)
  40 #define I2C_IFACE_1  ((volatile unsigned char *)&MADR2)
  41
  42 #define MAX_LOOP    0x100     /* TODO: select a better value */
  43
  44 /* PLLCR control */
  45 #define QSPISEL (1 << 11)               /* Selects QSPI or I2C interface */
  46
  47 /* Offsets to I2C registers from base address */
  48 #define O_MADR  0x00            /* Slave Address        */
  49 #define O_MFDR  0x04            /* Frequency divider    */
  50 #define O_MBCR  0x08            /* Control register     */
  51 #define O_MBSR  0x0c            /* Status register      */
  52 #define O_MBDR  0x10            /* Data register        */
  53
  54 /* MBSR - Status register */
  55 #define ICF     (1 << 7)        /* Transfer Complete    */
  56 #define IAAS    (1 << 6)        /* Addressed As Alave   */
  57 #define IBB     (1 << 5)        /* Bus Busy                     */
  58 #define IAL     (1 << 4)        /* Arbitration Lost         */
  59 #define SRW     (1 << 2)        /* Slave R/W                */
  60 #define IFF     (1 << 1)        /* I2C Interrupt            */
  61 #define RXAK    (1 << 0)        /* No Ack bit               */
  62
  63 /* MBCR - Control register */
  64 #define IEN     (1 << 7)                /* I2C Enable               */
  65 #define IIEN    (1 << 6)                /* Interrupt Enable         */
  66 #define MSTA    (1 << 5)                /* Master/Slave select  */
  67 #define MTX     (1 << 4)                /* Transmit/Receive         */
  68 #define TXAK    (1 << 3)                /* Transfer ACK             */
  69 #define RSTA    (1 << 2)                /* Restart..                */
  70
  71
  72 #endif