firmware/export/pp5020.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2004 by Thom Johansen
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef __PP5020_H__
  20 #define __PP5020_H__
  21
  22 /* All info gleaned and/or copied from the iPodLinux project. */
  23
  24 /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
  25 #define DRAM_START       0x10000000
  26
  27 /* Processor ID */
  28 #define PROCESSOR_ID     (*(volatile unsigned long *)(0x60000000))
  29
  30 #define PROC_ID_CPU      0x55
  31 #define PROC_ID_COP      0xaa
  32
  33 /* Mailboxes */
  34 #define MBX_BASE            (0x60001000)
  35 /* Read bits in the mailbox */
  36 #define MBX_MSG_STAT        (*(volatile unsigned long *)(0x60001000))
  37 /* Set bits in the mailbox */
  38 #define MBX_MSG_SET         (*(volatile unsigned long *)(0x60001004))
  39 /* Clear bits in the mailbox */
  40 #define MBX_MSG_CLR         (*(volatile unsigned long *)(0x60001008))
  41 /* Doesn't seem to be COP_REPLY at all :) */
  42 #define MBX_UNKNOWN1        (*(volatile unsigned long *)(0x6000100c))
  43 /* COP can set bit 29 - only CPU read clears it */
  44 #define CPU_QUEUE           (*(volatile unsigned long *)(0x60001010))
  45 /* CPU can set bit 29 - only COP read clears it */
  46 #define COP_QUEUE           (*(volatile unsigned long *)(0x60001020))
  47
  48 #define PROC_QUEUE(core)    ((&CPU_QUEUE)[(core)*4])
  49
  50 /* Interrupts */
  51 #define CPU_INT_STAT        (*(volatile unsigned long*)(0x60004000))
  52 #define COP_INT_STAT        (*(volatile unsigned long*)(0x60004004))
  53 #define CPU_FIQ_STAT        (*(volatile unsigned long*)(0x60004008))
  54 #define COP_FIQ_STAT        (*(volatile unsigned long*)(0x6000400c))
  55
  56 #define INT_STAT            (*(volatile unsigned long*)(0x60004010))
  57 #define INT_FORCED_STAT     (*(volatile unsigned long*)(0x60004014))
  58 #define INT_FORCED_SET      (*(volatile unsigned long*)(0x60004018))
  59 #define INT_FORCED_CLR      (*(volatile unsigned long*)(0x6000401c))
  60
  61 #define CPU_INT_EN_STAT     (*(volatile unsigned long*)(0x60004020))
  62 #define CPU_INT_EN          (*(volatile unsigned long*)(0x60004024))
  63 #define CPU_INT_CLR         (*(volatile unsigned long*)(0x60004028))
  64 #define CPU_INT_PRIORITY    (*(volatile unsigned long*)(0x6000402c))
  65
  66 #define COP_INT_EN_STAT     (*(volatile unsigned long*)(0x60004030))
  67 #define COP_INT_EN          (*(volatile unsigned long*)(0x60004034))
  68 #define COP_INT_CLR         (*(volatile unsigned long*)(0x60004038))
  69 #define COP_INT_PRIORITY    (*(volatile unsigned long*)(0x6000403c))
  70
  71 #define CPU_HI_INT_STAT     (*(volatile unsigned long*)(0x60004100))
  72 #define COP_HI_INT_STAT     (*(volatile unsigned long*)(0x60004104))
  73 #define CPU_HI_FIQ_STAT     (*(volatile unsigned long*)(0x60004108))
  74 #define COP_HI_FIQ_STAT     (*(volatile unsigned long*)(0x6000410c))
  75
  76 #define HI_INT_STAT         (*(volatile unsigned long*)(0x60004110))
  77 #define HI_INT_FORCED_STAT  (*(volatile unsigned long*)(0x60004114))
  78 #define HI_INT_FORCED_SET   (*(volatile unsigned long*)(0x60004118))
  79 #define HI_INT_FORCED_CLR   (*(volatile unsigned long*)(0x6000411c))
  80
  81 #define CPU_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004120))
  82 #define CPU_HI_INT_EN       (*(volatile unsigned long*)(0x60004124))
  83 #define CPU_HI_INT_CLR      (*(volatile unsigned long*)(0x60004128))
  84 #define CPU_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000412c))
  85
  86 #define COP_HI_INT_EN_STAT  (*(volatile unsigned long*)(0x60004130))
  87 #define COP_HI_INT_EN       (*(volatile unsigned long*)(0x60004134))
  88 #define COP_HI_INT_CLR      (*(volatile unsigned long*)(0x60004138))
  89 #define COP_HI_INT_PRIORITY (*(volatile unsigned long*)(0x6000413c))
  90
  91 #define TIMER1_IRQ   0
  92 #define TIMER2_IRQ   1
  93 #define MAILBOX_IRQ  4
  94 #define IIS_IRQ      10
  95 #define USB_IRQ      20
  96 #define IDE_IRQ      23
  97 #define FIREWIRE_IRQ 25
  98 #define HI_IRQ       30
  99 #define GPIO0_IRQ    (32+0) /* Ports A..D */
 100 #define GPIO1_IRQ    (32+1) /* Ports E..H */
 101 #define GPIO2_IRQ    (32+2) /* Ports I..L */
 102 #define SER0_IRQ     (32+4)
 103 #define SER1_IRQ     (32+5)
 104 #define I2C_IRQ      (32+8)
 105
 106 #define TIMER1_MASK   (1 << TIMER1_IRQ)
 107 #define TIMER2_MASK   (1 << TIMER2_IRQ)
 108 #define MAILBOX_MASK  (1 << MAILBOX_IRQ)
 109 #define IIS_MASK      (1 << IIS_IRQ)
 110 #define IDE_MASK      (1 << IDE_IRQ)
 111 #define USB_MASK      (1 << USB_IRQ)
 112 #define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
 113 #define HI_MASK       (1 << HI_IRQ)
 114 #define GPIO0_MASK    (1 << (GPIO0_IRQ-32))
 115 #define GPIO1_MASK    (1 << (GPIO1_IRQ-32))
 116 #define GPIO2_MASK    (1 << (GPIO2_IRQ-32))
 117 #define SER0_MASK     (1 << (SER0_IRQ-32))
 118 #define SER1_MASK     (1 << (SER1_IRQ-32))
 119 #define I2C_MASK      (1 << (I2C_IRQ-32))
 120
 121 /* Timers */
 122 #define TIMER1_CFG   (*(volatile unsigned long *)(0x60005000))
 123 #define TIMER1_VAL   (*(volatile unsigned long *)(0x60005004))
 124 #define TIMER2_CFG   (*(volatile unsigned long *)(0x60005008))
 125 #define TIMER2_VAL   (*(volatile unsigned long *)(0x6000500c))
 126 #define USEC_TIMER   (*(volatile unsigned long *)(0x60005010))
 127 #define RTC          (*(volatile unsigned long *)(0x60005014))
 128
 129 /* Device Controller */
 130 #define DEV_RS       (*(volatile unsigned long *)(0x60006004))
 131 #define DEV_RS2      (*(volatile unsigned long *)(0x60006008))
 132 #define DEV_EN       (*(volatile unsigned long *)(0x6000600c))
 133 #define DEV_EN2      (*(volatile unsigned long *)(0x60006010))
 134
 135 #define DEV_EXTCLOCKS   0x00000002
 136 #define DEV_SYSTEM      0x00000004
 137 #define DEV_USB0        0x00000008
 138 #define DEV_SER0        0x00000040
 139 #define DEV_SER1        0x00000080
 140 #define DEV_I2S         0x00000800
 141 #define DEV_I2C         0x00001000
 142 #define DEV_ATA         0x00004000
 143 #define DEV_OPTO        0x00010000
 144 #define DEV_PIEZO       0x00010000
 145 #define DEV_PWM         0x00020000
 146 #define DEV_USB1        0x00400000
 147 #define DEV_FIREWIRE    0x00800000
 148 #define DEV_IDE0        0x02000000
 149 #define DEV_LCD         0x04000000
 150
 151 /* clock control */
 152 #define CLOCK_SOURCE    (*(volatile unsigned long *)(0x60006020))
 153 #define MLCD_SCLK_DIV   (*(volatile unsigned long *)(0x6000602c))
 154         /* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
 155 #define PLL_CONTROL     (*(volatile unsigned long *)(0x60006034))
 156 #define PLL_STATUS      (*(volatile unsigned long *)(0x6000603c))
 157 #define ADC_CLOCK_SRC   (*(volatile unsigned long *)(0x60006094))
 158 #define CLCD_CLOCK_SRC  (*(volatile unsigned long *)(0x600060a0))
 159
 160 /* Processors Control */
 161 #define CPU_CTL          (*(volatile unsigned long *)(0x60007000))
 162 #define COP_CTL          (*(volatile unsigned long *)(0x60007004))
 163 #define PROC_CTL(core)   ((&CPU_CTL)[core])
 164
 165 #define PROC_SLEEP     0x80000000
 166 #define PROC_WAIT      0x40000000
 167 #define PROC_WAIT_CLR  0x20000000
 168 #define PROC_CNT_START 0x08000000
 169 #define PROC_WAKE      0x00000000
 170 /**
 171  * This is based on some quick but sound experiments on PP5022C.
 172  * CPU/COP_CTL bitmap:
 173  *   [31] - sleep until an interrupt occurs
 174  *   [30] - wait for cycle countdown to 0
 175  *   [29] - wait for cycle countdown to 0
 176  *          behaves identically to bit 30 unless bit 30 is set as well
 177  *          in which case this bit is cleared at the end of the count
 178  *   [28] - unknown - no execution effect observed yet
 179  *   [27] - begin cycle countdown
 180  * [26:8] - semaphore flags for core communication ?
 181  *          no execution effect observed yet
 182  *          [11:8] seem to often be set to the core's own ID
 183  *                 nybble when sleeping - 0x5 or 0xa.
 184  *  [7:0] - W: number of cycles to skip on next instruction
 185  *          R: cycles remaining
 186  * Executing on CPU
 187  *   CPU_CTL = 0x68000080
 188  *   nop
 189  * stalls the nop for 128 cycles
 190  * Reading CPU_CTL after the nop will return 0x48000000
 191  */
 192
 193 /* Cache Control */
 194 #define CACHE_PRIORITY   (*(volatile unsigned long *)(0x60006044))
 195 #define CACHE_CTL        (*(volatile unsigned long *)(0x6000c000))
 196 #define CACHE_MASK       (*(volatile unsigned long *)(0xf000f040))
 197 #define CACHE_OPERATION  (*(volatile unsigned long *)(0xf000f044))
 198 #define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
 199
 200 /* CACHE_CTL bits */
 201 #define CACHE_CTL_DISABLE    0x0000
 202 #define CACHE_CTL_ENABLE     0x0001
 203 #define CACHE_CTL_RUN        0x0002
 204 #define CACHE_CTL_INIT       0x0004
 205 #define CACHE_CTL_VECT_REMAP 0x0010
 206 #define CACHE_CTL_READY      0x4000
 207 #define CACHE_CTL_BUSY       0x8000
 208 /* CACHE_OPERATION bits */
 209 #define CACHE_OP_FLUSH       0x0002
 210 #define CACHE_OP_INVALIDATE  0x0004
 211
 212 /* GPIO Ports */
 213 #define GPIOA_ENABLE     (*(volatile unsigned long *)(0x6000d000))
 214 #define GPIOB_ENABLE     (*(volatile unsigned long *)(0x6000d004))
 215 #define GPIOC_ENABLE     (*(volatile unsigned long *)(0x6000d008))
 216 #define GPIOD_ENABLE     (*(volatile unsigned long *)(0x6000d00c))
 217 #define GPIOA_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d010))
 218 #define GPIOB_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d014))
 219 #define GPIOC_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d018))
 220 #define GPIOD_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d01c))
 221 #define GPIOA_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d020))
 222 #define GPIOB_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d024))
 223 #define GPIOC_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d028))
 224 #define GPIOD_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d02c))
 225 #define GPIOA_INPUT_VAL  (*(volatile unsigned long *)(0x6000d030))
 226 #define GPIOB_INPUT_VAL  (*(volatile unsigned long *)(0x6000d034))
 227 #define GPIOC_INPUT_VAL  (*(volatile unsigned long *)(0x6000d038))
 228 #define GPIOD_INPUT_VAL  (*(volatile unsigned long *)(0x6000d03c))
 229 #define GPIOA_INT_STAT   (*(volatile unsigned long *)(0x6000d040))
 230 #define GPIOB_INT_STAT   (*(volatile unsigned long *)(0x6000d044))
 231 #define GPIOC_INT_STAT   (*(volatile unsigned long *)(0x6000d048))
 232 #define GPIOD_INT_STAT   (*(volatile unsigned long *)(0x6000d04c))
 233 #define GPIOA_INT_EN     (*(volatile unsigned long *)(0x6000d050))
 234 #define GPIOB_INT_EN     (*(volatile unsigned long *)(0x6000d054))
 235 #define GPIOC_INT_EN     (*(volatile unsigned long *)(0x6000d058))
 236 #define GPIOD_INT_EN     (*(volatile unsigned long *)(0x6000d05c))
 237 #define GPIOA_INT_LEV    (*(volatile unsigned long *)(0x6000d060))
 238 #define GPIOB_INT_LEV    (*(volatile unsigned long *)(0x6000d064))
 239 #define GPIOC_INT_LEV    (*(volatile unsigned long *)(0x6000d068))
 240 #define GPIOD_INT_LEV    (*(volatile unsigned long *)(0x6000d06c))
 241 #define GPIOA_INT_CLR    (*(volatile unsigned long *)(0x6000d070))
 242 #define GPIOB_INT_CLR    (*(volatile unsigned long *)(0x6000d074))
 243 #define GPIOC_INT_CLR    (*(volatile unsigned long *)(0x6000d078))
 244 #define GPIOD_INT_CLR    (*(volatile unsigned long *)(0x6000d07c))
 245
 246 #define GPIOE_ENABLE     (*(volatile unsigned long *)(0x6000d080))
 247 #define GPIOF_ENABLE     (*(volatile unsigned long *)(0x6000d084))
 248 #define GPIOG_ENABLE     (*(volatile unsigned long *)(0x6000d088))
 249 #define GPIOH_ENABLE     (*(volatile unsigned long *)(0x6000d08c))
 250 #define GPIOE_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d090))
 251 #define GPIOF_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d094))
 252 #define GPIOG_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d098))
 253 #define GPIOH_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d09c))
 254 #define GPIOE_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a0))
 255 #define GPIOF_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a4))
 256 #define GPIOG_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0a8))
 257 #define GPIOH_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d0ac))
 258 #define GPIOE_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b0))
 259 #define GPIOF_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b4))
 260 #define GPIOG_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0b8))
 261 #define GPIOH_INPUT_VAL  (*(volatile unsigned long *)(0x6000d0bc))
 262 #define GPIOE_INT_STAT   (*(volatile unsigned long *)(0x6000d0c0))
 263 #define GPIOF_INT_STAT   (*(volatile unsigned long *)(0x6000d0c4))
 264 #define GPIOG_INT_STAT   (*(volatile unsigned long *)(0x6000d0c8))
 265 #define GPIOH_INT_STAT   (*(volatile unsigned long *)(0x6000d0cc))
 266 #define GPIOE_INT_EN     (*(volatile unsigned long *)(0x6000d0d0))
 267 #define GPIOF_INT_EN     (*(volatile unsigned long *)(0x6000d0d4))
 268 #define GPIOG_INT_EN     (*(volatile unsigned long *)(0x6000d0d8))
 269 #define GPIOH_INT_EN     (*(volatile unsigned long *)(0x6000d0dc))
 270 #define GPIOE_INT_LEV    (*(volatile unsigned long *)(0x6000d0e0))
 271 #define GPIOF_INT_LEV    (*(volatile unsigned long *)(0x6000d0e4))
 272 #define GPIOG_INT_LEV    (*(volatile unsigned long *)(0x6000d0e8))
 273 #define GPIOH_INT_LEV    (*(volatile unsigned long *)(0x6000d0ec))
 274 #define GPIOE_INT_CLR    (*(volatile unsigned long *)(0x6000d0f0))
 275 #define GPIOF_INT_CLR    (*(volatile unsigned long *)(0x6000d0f4))
 276 #define GPIOG_INT_CLR    (*(volatile unsigned long *)(0x6000d0f8))
 277 #define GPIOH_INT_CLR    (*(volatile unsigned long *)(0x6000d0fc))
 278
 279 #define GPIOI_ENABLE     (*(volatile unsigned long *)(0x6000d100))
 280 #define GPIOJ_ENABLE     (*(volatile unsigned long *)(0x6000d104))
 281 #define GPIOK_ENABLE     (*(volatile unsigned long *)(0x6000d108))
 282 #define GPIOL_ENABLE     (*(volatile unsigned long *)(0x6000d10c))
 283 #define GPIOI_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d110))
 284 #define GPIOJ_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d114))
 285 #define GPIOK_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d118))
 286 #define GPIOL_OUTPUT_EN  (*(volatile unsigned long *)(0x6000d11c))
 287 #define GPIOI_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d120))
 288 #define GPIOJ_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d124))
 289 #define GPIOK_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d128))
 290 #define GPIOL_OUTPUT_VAL (*(volatile unsigned long *)(0x6000d12c))
 291 #define GPIOI_INPUT_VAL  (*(volatile unsigned long *)(0x6000d130))
 292 #define GPIOJ_INPUT_VAL  (*(volatile unsigned long *)(0x6000d134))
 293 #define GPIOK_INPUT_VAL  (*(volatile unsigned long *)(0x6000d138))
 294 #define GPIOL_INPUT_VAL  (*(volatile unsigned long *)(0x6000d13c))
 295 #define GPIOI_INT_STAT   (*(volatile unsigned long *)(0x6000d140))
 296 #define GPIOJ_INT_STAT   (*(volatile unsigned long *)(0x6000d144))
 297 #define GPIOK_INT_STAT   (*(volatile unsigned long *)(0x6000d148))
 298 #define GPIOL_INT_STAT   (*(volatile unsigned long *)(0x6000d14c))
 299 #define GPIOI_INT_EN     (*(volatile unsigned long *)(0x6000d150))
 300 #define GPIOJ_INT_EN     (*(volatile unsigned long *)(0x6000d154))
 301 #define GPIOK_INT_EN     (*(volatile unsigned long *)(0x6000d158))
 302 #define GPIOL_INT_EN     (*(volatile unsigned long *)(0x6000d15c))
 303 #define GPIOI_INT_LEV    (*(volatile unsigned long *)(0x6000d160))
 304 #define GPIOJ_INT_LEV    (*(volatile unsigned long *)(0x6000d164))
 305 #define GPIOK_INT_LEV    (*(volatile unsigned long *)(0x6000d168))
 306 #define GPIOL_INT_LEV    (*(volatile unsigned long *)(0x6000d16c))
 307 #define GPIOI_INT_CLR    (*(volatile unsigned long *)(0x6000d170))
 308 #define GPIOJ_INT_CLR    (*(volatile unsigned long *)(0x6000d174))
 309 #define GPIOK_INT_CLR    (*(volatile unsigned long *)(0x6000d178))
 310 #define GPIOL_INT_CLR    (*(volatile unsigned long *)(0x6000d17c))
 311
 312 /* Standard GPIO addresses + 0x800 allow atomic port manipulation on PP502x.
 313  * Bits 8..15 of the written word define which bits are changed, bits 0..7
 314  * define the value of those bits. */
 315
 316 #define GPIO_SET_BITWISE(port, mask) \
 317         do { *(&port + (0x800/sizeof(long))) = (mask << 8) | mask; } while(0)
 318
 319 #define GPIO_CLEAR_BITWISE(port, mask) \
 320         do { *(&port + (0x800/sizeof(long))) = mask << 8; } while(0)
 321
 322 /* Device initialization */
 323 #define PP_VER1          (*(volatile unsigned long *)(0x70000000))
 324 #define PP_VER2          (*(volatile unsigned long *)(0x70000004))
 325 #define STRAP_OPT_A      (*(volatile unsigned long *)(0x70000008))
 326 #define STRAP_OPT_B      (*(volatile unsigned long *)(0x7000000c))
 327 #define BUS_WIDTH_MASK   0x00000010
 328 #define RAM_TYPE_MASK    0x000000c0
 329 #define ROM_TYPE_MASK    0x00000008
 330
 331 #define DEV_INIT1        (*(volatile unsigned long *)(0x70000010))
 332 #define DEV_INIT2        (*(volatile unsigned long *)(0x70000020))
 333 /* some timing that needs to be handled during clock setup */
 334 #define DEV_TIMING1      (*(volatile unsigned long *)(0x70000034))
 335 #define XMB_NOR_CFG      (*(volatile unsigned long *)(0x70000038))
 336 #define XMB_RAM_CFG      (*(volatile unsigned long *)(0x7000003c))
 337
 338 #define INIT_BUTTONS     0x00040000
 339 #define INIT_PLL         0x40000000
 340 #define INIT_USB         0x80000000
 341
 342 /* 32 bit GPO port */
 343 #define GPO32_VAL        (*(volatile unsigned long *)(0x70000080))
 344 #define GPO32_ENABLE     (*(volatile unsigned long *)(0x70000084))
 345
 346 /* IIS */
 347 #define IISDIV              (*(volatile unsigned long*)(0x60006080))
 348 #define IISCONFIG           (*(volatile unsigned long*)(0x70002800))
 349 #define IISCLK              (*(volatile unsigned long*)(0x70002808))
 350 #define IISFIFO_CFG         (*(volatile unsigned long*)(0x7000280c))
 351 #define IISFIFO_WR          (*(volatile unsigned long*)(0x70002840))
 352 #define IISFIFO_WRH         (*(volatile unsigned short*)(0x70002840))
 353 #define IISFIFO_RD          (*(volatile unsigned long*)(0x70002880))
 354 #define IISFIFO_RDH         (*(volatile unsigned short*)(0x70002880))
 355
 356 /**
 357  * IISCONFIG bits:
 358  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 359  * | RESET  |        |TXFIFOEN|RXFIFOEN|        |  ????  |   MS   |  ????  |
 360  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 361  * |        |        |        |        |        |        |        |        |
 362  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 363  * |        |        |        |        | Bus Format[1:0] |     Size[1:0]   |
 364  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 365  * |        |     Size Format[2:0]     |  ????  |  ????  | IRQTX  | IRQRX  |
 366  */
 367
 368 /* All IIS formats send MSB first */
 369 #define IIS_RESET    (1 << 31)
 370 #define IIS_TXFIFOEN (1 << 29)
 371 #define IIS_RXFIFOEN (1 << 28)
 372 #define IIS_MASTER   (1 << 25)
 373 #define IIS_IRQTX    (1 << 1)
 374 #define IIS_IRQRX    (1 << 0)
 375
 376 #define IIS_IRQTX_REG  IISCONFIG
 377 #define IIS_IRQRX_REG  IISCONFIG
 378
 379 /* Data format on the IIS bus */
 380 #define IIS_FORMAT_MASK  (0x3 << 10)
 381 #define IIS_FORMAT_IIS   (0x0 << 10) /* Standard IIS - leading dummy bit */
 382 #define IIS_FORMAT_1     (0x1 << 10)
 383 #define IIS_FORMAT_LJUST (0x2 << 10) /* Left justified - no dummy bit */
 384 #define IIS_FORMAT_3     (0x3 << 10)
 385 /* Other formats not yet known  */
 386
 387 /* Data size on IIS bus */
 388 #define IIS_SIZE_MASK   (0x3 << 8)
 389 #define IIS_SIZE_16BIT  (0x0 << 8)
 390 /* Other sizes not yet known */
 391
 392 /* Data size/format on IIS FIFO */
 393 #define IIS_FIFO_FORMAT_MASK        (0x7 << 4)
 394 #define IIS_FIFO_FORMAT_LE_HALFWORD (0x0 << 4)
 395 /* Big-endian formats - data sent to the FIFO must be big endian.
 396  * I forgot which is which size but did test them. */
 397 #define IIS_FIFO_FORMAT_1           (0x1 << 4)
 398 #define IIS_FIFO_FORMAT_2           (0x2 << 4)
 399 /* 32bit-MSB-little endian */
 400 #define IIS_FIFO_FORMAT_LE32        (0x3 << 4)
 401 /* 16bit-MSB-little endian */
 402 #define IIS_FIFO_FORMAT_LE16        (0x4 << 4)
 403 #define IIS_FIFO_FORMAT_5           (0x5 << 4)
 404 #define IIS_FIFO_FORMAT_6           (0x6 << 4)
 405 /* A second one like IIS_FIFO_FORMAT_LE16? PP5020 only? */
 406 #define IIS_FIFO_FORMAT_LE16_2      (0x7 << 4)
 407
 408 /* FIFO formats 0x5 and above seem equivalent to 0x4 ?? */
 409
 410 /**
 411  * IISFIFO_CFG bits:
 412  * |   31   |   30   |   29   |   28   |   27   |   26   |   25   |   24   |
 413  * |        |        |                      RXFull[5:0]                    |
 414  * |   23   |   22   |   21   |   20   |   19   |   18   |   17   |   16   |
 415  * |        |        |                      TXFree[5:0]                    |
 416  * |   15   |   14   |   13   |   12   |   11   |   10   |    9   |    8   |
 417  * |        |        |        | RXCLR  |        |        |        | TXCLR  |
 418  * |    7   |    6   |    5   |    4   |    3   |    2   |    1   |    0   |
 419  * |        |        |   RX_FULL_LVL   |        |        |  TX_EMPTY_LVL   |
 420  */
 421
 422 /* handy macros to extract the FIFO counts */
 423 #define IIS_RX_FULL_MASK (0x3f << 24)
 424 #define IIS_RX_FULL_COUNT \
 425     ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 24)
 426
 427 #define IIS_TX_FREE_MASK (0x3f << 16)
 428 #define IIS_TX_FREE_COUNT \
 429     ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 16)
 430
 431 #define IIS_RXCLR (1 << 12)
 432 #define IIS_TXCLR (1 << 8)
 433 /* Number of slots */
 434 #define IIS_RX_FULL_LVL_4  (0x1 << 4)
 435 #define IIS_RX_FULL_LVL_8  (0x2 << 4)
 436 #define IIS_RX_FULL_LVL_12 (0x3 << 4)
 437
 438 #define IIS_TX_EMPTY_LVL_4  (0x1 << 0)
 439 #define IIS_TX_EMPTY_LVL_8  (0x2 << 0)
 440 #define IIS_TX_EMPTY_LVL_12 (0x3 << 0)
 441
 442 /* Note: didn't bother to see of levels 0 and 16 actually work */
 443
 444 /* First ("mono") LCD bridge */
 445 #define LCD1_BASE           0x70003000
 446
 447 #define LCD1_CONTROL        (*(volatile unsigned long *)(0x70003000))
 448 #define LCD1_CMD            (*(volatile unsigned long *)(0x70003008))
 449 #define LCD1_DATA           (*(volatile unsigned long *)(0x70003010))
 450
 451 #define LCD1_BUSY_MASK      0x8000
 452
 453 /* Serial Controller */
 454 #define SER0_BASE           (*(volatile unsigned long*)(0x70006000))
 455
 456 #define SER0_RBR            (*(volatile unsigned long*)(0x70006000))
 457 #define SER0_THR            (*(volatile unsigned long*)(0x70006000))
 458 #define SER0_IER            (*(volatile unsigned long*)(0x70006004))
 459 #define SER0_FCR            (*(volatile unsigned long*)(0x70006008))
 460 #define SER0_IIR            (*(volatile unsigned long*)(0x70006008))
 461 #define SER0_LCR            (*(volatile unsigned long*)(0x7000600c))
 462 #define SER0_MCR            (*(volatile unsigned long*)(0x70006010))
 463 #define SER0_LSR            (*(volatile unsigned long*)(0x70006014))
 464 #define SER0_MSR            (*(volatile unsigned long*)(0x70006018))
 465 #define SER0_SPR            (*(volatile unsigned long*)(0x7000601c))
 466
 467 #define SER0_DLL            (*(volatile unsigned long*)(0x70006000))
 468 #define SER0_DLM            (*(volatile unsigned long*)(0x70006004))
 469
 470 #define SER1_BASE           (*(volatile unsigned long*)(0x70006040))
 471
 472 #define SER1_RBR            (*(volatile unsigned long*)(0x70006040))
 473 #define SER1_THR            (*(volatile unsigned long*)(0x70006040))
 474 #define SER1_IER            (*(volatile unsigned long*)(0x70006044))
 475 #define SER1_FCR            (*(volatile unsigned long*)(0x70006048))
 476 #define SER1_IIR            (*(volatile unsigned long*)(0x70006048))
 477 #define SER1_LCR            (*(volatile unsigned long*)(0x7000604c))
 478 #define SER1_MCR            (*(volatile unsigned long*)(0x70006050))
 479 #define SER1_LSR            (*(volatile unsigned long*)(0x70006054))
 480 #define SER1_MSR            (*(volatile unsigned long*)(0x70006058))
 481 #define SER1_SPR            (*(volatile unsigned long*)(0x7000605c))
 482
 483 #define SER1_DLL            (*(volatile unsigned long*)(0x70006040))
 484 #define SER1_DLM            (*(volatile unsigned long*)(0x70006044))
 485
 486 /* Second ("color") LCD bridge */
 487 #define LCD2_BASE           0x70008a00
 488
 489 #define LCD2_PORT           (*(volatile unsigned long*)(0x70008a0c))
 490 #define LCD2_BLOCK_CTRL     (*(volatile unsigned long*)(0x70008a20))
 491 #define LCD2_BLOCK_CONFIG   (*(volatile unsigned long*)(0x70008a24))
 492 #define LCD2_BLOCK_DATA     (*(volatile unsigned long*)(0x70008b00))
 493
 494 #define LCD2_BUSY_MASK      0x80000000
 495 #define LCD2_CMD_MASK       0x80000000
 496 #define LCD2_DATA_MASK      0x81000000
 497
 498 #define LCD2_BLOCK_READY    0x04000000
 499 #define LCD2_BLOCK_TXOK     0x01000000
 500
 501 /* I2C */
 502 #define I2C_BASE            0x7000c000
 503
 504 /* EIDE Controller */
 505 #define IDE_BASE            0xc3000000
 506
 507 #define IDE0_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000000))
 508 #define IDE0_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000004))
 509 #define IDE0_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000008))
 510 #define IDE0_SEC_TIMING1    (*(volatile unsigned long*)(0xc300000c))
 511
 512 #define IDE1_PRI_TIMING0    (*(volatile unsigned long*)(0xc3000010))
 513 #define IDE1_PRI_TIMING1    (*(volatile unsigned long*)(0xc3000014))
 514 #define IDE1_SEC_TIMING0    (*(volatile unsigned long*)(0xc3000018))
 515 #define IDE1_SEC_TIMING1    (*(volatile unsigned long*)(0xc300001c))
 516
 517 #define IDE0_CFG            (*(volatile unsigned long*)(0xc3000028))
 518 #define IDE1_CFG            (*(volatile unsigned long*)(0xc300002c))
 519
 520 #define IDE0_CNTRLR_STAT    (*(volatile unsigned long*)(0xc30001e0))
 521
 522 /* USB controller */
 523 #define USB_BASE            0xc5000000
 524
 525 /* Firewire Controller */
 526 #define FIREWIRE_BASE       0xc6000000
 527
 528 /* Memory controller */
 529 #define CACHE_BASE              (*(volatile unsigned long*)(0xf0000000))
 530 /* 0xf0000000-0xf0001fff */
 531 #define CACHE_DATA_BASE         (*(volatile unsigned long*)(0xf0000000))
 532 /* 0xf0002000-0xf0003fff */
 533 #define CACHE_DATA_MIRROR_BASE  (*(volatile unsigned long*)(0xf0002000))
 534 /* 0xf0004000-0xf0007fff */
 535 #define CACHE_STATUS_BASE       (*(volatile unsigned long*)(0xf0004000))
 536 #define CACHE_FLUSH_BASE        (*(volatile unsigned long*)(0xf0008000))
 537 #define CACHE_INVALID_BASE      (*(volatile unsigned long*)(0xf000c000))
 538 #define MMAP_PHYS_READ_MASK     0x0100
 539 #define MMAP_PHYS_WRITE_MASK    0x0200
 540 #define MMAP_PHYS_DATA_MASK     0x0400
 541 #define MMAP_PHYS_CODE_MASK     0x0800
 542 #define MMAP_FIRST              (*(volatile unsigned long*)(0xf000f000))
 543 #define MMAP_LAST               (*(volatile unsigned long*)(0xf000f03c))
 544 #define MMAP0_LOGICAL           (*(volatile unsigned long*)(0xf000f000))
 545 #define MMAP0_PHYSICAL          (*(volatile unsigned long*)(0xf000f004))
 546 #define MMAP1_LOGICAL           (*(volatile unsigned long*)(0xf000f008))
 547 #define MMAP1_PHYSICAL          (*(volatile unsigned long*)(0xf000f00c))
 548 #define MMAP2_LOGICAL           (*(volatile unsigned long*)(0xf000f010))
 549 #define MMAP2_PHYSICAL          (*(volatile unsigned long*)(0xf000f014))
 550 #define MMAP3_LOGICAL           (*(volatile unsigned long*)(0xf000f018))
 551 #define MMAP3_PHYSICAL          (*(volatile unsigned long*)(0xf000f01c))
 552 #define MMAP4_LOGICAL           (*(volatile unsigned long*)(0xf000f020))
 553 #define MMAP4_PHYSICAL          (*(volatile unsigned long*)(0xf000f024))
 554 #define MMAP5_LOGICAL           (*(volatile unsigned long*)(0xf000f028))
 555 #define MMAP5_PHYSICAL          (*(volatile unsigned long*)(0xf000f02c))
 556 #define MMAP6_LOGICAL           (*(volatile unsigned long*)(0xf000f030))
 557 #define MMAP6_PHYSICAL          (*(volatile unsigned long*)(0xf000f034))
 558 #define MMAP7_LOGICAL           (*(volatile unsigned long*)(0xf000f038))
 559 #define MMAP7_PHYSICAL          (*(volatile unsigned long*)(0xf000f03c))
 560
 561 #endif /* __PP5020_H__ */