apps/codecs/spc/spc_emu.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006-2007 Adam Gashlin (hcs)
  11  * Copyright (C) 2004-2007 Shay Green (blargg)
  12  * Copyright (C) 2002 Brad Martin
  13  *
  14  * All files in this archive are subject to the GNU General Public License.
  15  * See the file COPYING in the source tree root for full license agreement.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "codec.h"
  22 #include "codecs.h"
  23 #include "spc_codec.h"
  24 #include "spc_profiler.h"
  25
  26 /* lovingly ripped off from Game_Music_Emu 0.5.2. http://www.slack.net/~ant/ */
  27 /* DSP Based on Brad Martin's OpenSPC DSP emulator */
  28 /* tag reading from sexyspc by John Brawn (John_Brawn@yahoo.com) and others */
  29
  30 struct cpu_ram_t ram CACHEALIGN_ATTR;
  31
  32 /**************** Timers ****************/
  33
  34 void Timer_run_( struct Timer* t, long time )
  35 {
  36     /* when disabled, next_tick should always be in the future */
  37     assert( t->enabled );
  38
  39     int elapsed = ((time - t->next_tick) >> t->shift) + 1;
  40     t->next_tick += elapsed << t->shift;
  41
  42     elapsed += t->count;
  43     if ( elapsed >= t->period ) /* avoid unnecessary division */
  44     {
  45         int n = elapsed / t->period;
  46         elapsed -= n * t->period;
  47         t->counter = (t->counter + n) & 15;
  48     }
  49     t->count = elapsed;
  50 }
  51
  52 /**************** SPC emulator ****************/
  53 /* 1.024 MHz clock / 32000 samples per second */
  54
  55 static void SPC_enable_rom( THIS, int enable )
  56 {
  57     if ( this->rom_enabled != enable )
  58     {
  59         this->rom_enabled = enable;
  60         ci->memcpy( RAM + ROM_ADDR, (enable ? this->boot_rom : this->extra_ram), ROM_SIZE );
  61         /* TODO: ROM can still get overwritten when DSP writes to echo buffer */
  62     }
  63 }
  64
  65 void SPC_Init( THIS )
  66 {
  67     this->timer [0].shift = 4 + 3; /* 8 kHz */
  68     this->timer [1].shift = 4 + 3; /* 8 kHz */
  69     this->timer [2].shift = 4; /* 8 kHz */
  70
  71     /* Put STOP instruction around memory to catch PC underflow/overflow. */
  72     ci->memset( ram.padding1, 0xFF, sizeof ram.padding1 );
  73     ci->memset( ram.padding2, 0xFF, sizeof ram.padding2 );
  74
  75     /* A few tracks read from the last four bytes of IPL ROM */
  76     this->boot_rom [sizeof this->boot_rom - 2] = 0xC0;
  77     this->boot_rom [sizeof this->boot_rom - 1] = 0xFF;
  78     ci->memset( this->boot_rom, 0, sizeof this->boot_rom - 2 );
  79
  80     /* Have DSP in a defined state in case EMU is run and hasn't loaded
  81      * a program yet */
  82     DSP_reset(&this->dsp);
  83 }
  84
  85 static void SPC_load_state( THIS, struct cpu_regs_t const* cpu_state,
  86         const void* new_ram, const void* dsp_state )
  87 {
  88     ci->memcpy(&(this->r),cpu_state,sizeof this->r);
  89
  90     /* ram */
  91     ci->memcpy( RAM, new_ram, sizeof RAM );
  92     ci->memcpy( this->extra_ram, RAM + ROM_ADDR, sizeof this->extra_ram );
  93
  94     /* boot rom (have to force enable_rom() to update it) */
  95     this->rom_enabled = !(RAM [0xF1] & 0x80);
  96     SPC_enable_rom( this, !this->rom_enabled );
  97
  98     /* dsp */
  99     /* some SPCs rely on DSP immediately generating one sample */
 100     this->extra_cycles = 32;
 101     DSP_reset( &this->dsp );
 102     int i;
 103     for ( i = 0; i < REGISTER_COUNT; i++ )
 104         DSP_write( &this->dsp, i, ((uint8_t const*) dsp_state) [i] );
 105
 106     /* timers */
 107     for ( i = 0; i < TIMER_COUNT; i++ )
 108     {
 109         struct Timer* t = &this->timer [i];
 110
 111         t->next_tick = -EXTRA_CLOCKS;
 112         t->enabled = (RAM [0xF1] >> i) & 1;
 113         if ( !t->enabled )
 114             t->next_tick = TIMER_DISABLED_TIME;
 115         t->count = 0;
 116         t->counter = RAM [0xFD + i] & 15;
 117
 118         int p = RAM [0xFA + i];
 119         if ( !p )
 120             p = 0x100;
 121         t->period = p;
 122     }
 123
 124     /* Handle registers which already give 0 when read by
 125        setting RAM and not changing it.
 126        Put STOP instruction in registers which can be read,
 127        to catch attempted execution. */
 128     RAM [0xF0] = 0;
 129     RAM [0xF1] = 0;
 130     RAM [0xF3] = 0xFF;
 131     RAM [0xFA] = 0;
 132     RAM [0xFB] = 0;
 133     RAM [0xFC] = 0;
 134     RAM [0xFD] = 0xFF;
 135     RAM [0xFE] = 0xFF;
 136     RAM [0xFF] = 0xFF;
 137 }
 138
 139 static void clear_echo( THIS )
 140 {
 141     if ( !(DSP_read( &this->dsp, 0x6C ) & 0x20) )
 142     {
 143         unsigned addr = 0x100 * DSP_read( &this->dsp, 0x6D );
 144         size_t   size = 0x800 * DSP_read( &this->dsp, 0x7D );
 145         size_t max_size = sizeof RAM - addr;
 146         if ( size > max_size )
 147             size = sizeof RAM - addr;
 148         ci->memset( RAM + addr, 0xFF, size );
 149     }
 150 }
 151
 152 int SPC_load_spc( THIS, const void* data, long size )
 153 {
 154     struct spc_file_t const* spc = (struct spc_file_t const*) data;
 155     struct cpu_regs_t regs;
 156
 157     if ( size < SPC_FILE_SIZE )
 158         return -1;
 159
 160     if ( ci->memcmp( spc->signature, "SNES-SPC700 Sound File Data", 27 ) != 0 )
 161         return -1;
 162
 163     regs.pc     = spc->pc [1] * 0x100 + spc->pc [0];
 164     regs.a      = spc->a;
 165     regs.x      = spc->x;
 166     regs.y      = spc->y;
 167     regs.status = spc->status;
 168     regs.sp     = spc->sp;
 169
 170     if ( (unsigned long) size >= sizeof *spc )
 171         ci->memcpy( this->boot_rom, spc->ipl_rom, sizeof this->boot_rom );
 172
 173     SPC_load_state( this, &regs, spc->ram, spc->dsp );
 174
 175     clear_echo(this);
 176
 177     return 0;
 178 }
 179
 180 /**************** DSP interaction ****************/
 181 void SPC_run_dsp_( THIS, long time )
 182 {
 183     /* divide by CLOCKS_PER_SAMPLE */
 184     int count = ((time - this->next_dsp) >> 5) + 1;
 185     int32_t* buf = this->sample_buf;
 186     this->sample_buf = buf + count;
 187     this->next_dsp += count * CLOCKS_PER_SAMPLE;
 188     DSP_run( &this->dsp, count, buf );
 189 }
 190
 191 int SPC_read( THIS, unsigned addr, long const time )
 192 {
 193     int result = RAM [addr];
 194
 195     if ( ((unsigned) (addr - 0xF0)) < 0x10 )
 196     {
 197         assert( 0xF0 <= addr && addr <= 0xFF );
 198
 199         /* counters */
 200         int i = addr - 0xFD;
 201         if ( i >= 0 )
 202         {
 203             struct Timer* t = &this->timer [i];
 204             Timer_run( t, time );
 205             result = t->counter;
 206             t->counter = 0;
 207         }
 208         /* dsp */
 209         else if ( addr == 0xF3 )
 210         {
 211             SPC_run_dsp( this, time );
 212             result = DSP_read( &this->dsp, RAM [0xF2] & 0x7F );
 213         }
 214     }
 215     return result;
 216 }
 217
 218 void SPC_write( THIS, unsigned addr, int data, long const time )
 219 {
 220     /* first page is very common */
 221     if ( addr < 0xF0 )
 222     {
 223         RAM [addr] = (uint8_t) data;
 224     }
 225     else switch ( addr )
 226     {
 227         /* RAM */
 228         default:
 229             if ( addr < ROM_ADDR )
 230             {
 231                 RAM [addr] = (uint8_t) data;
 232             }
 233             else
 234             {
 235                 this->extra_ram [addr - ROM_ADDR] = (uint8_t) data;
 236                 if ( !this->rom_enabled )
 237                     RAM [addr] = (uint8_t) data;
 238             }
 239             break;
 240
 241         /* DSP */
 242         /*case 0xF2:*/ /* mapped to RAM */
 243         case 0xF3: {
 244             SPC_run_dsp( this, time );
 245             int reg = RAM [0xF2];
 246             if ( reg < REGISTER_COUNT ) {
 247                 DSP_write( &this->dsp, reg, data );
 248             }
 249             else {
 250                 /*dprintf( "DSP write to $%02X\n", (int) reg ); */
 251             }
 252             break;
 253         }
 254
 255         case 0xF0: /* Test register */
 256             /*dprintf( "Wrote $%02X to $F0\n", (int) data ); */
 257             break;
 258
 259         /* Config */
 260         case 0xF1:
 261         {
 262             int i;
 263             /* timers */
 264             for ( i = 0; i < TIMER_COUNT; i++ )
 265             {
 266                 struct Timer * t = this->timer+i;
 267                 if ( !(data & (1 << i)) )
 268                 {
 269                     t->enabled = 0;
 270                     t->next_tick = TIMER_DISABLED_TIME;
 271                 }
 272                 else if ( !t->enabled )
 273                 {
 274                     /* just enabled */
 275                     t->enabled = 1;
 276                     t->counter = 0;
 277                     t->count = 0;
 278                     t->next_tick = time;
 279                 }
 280             }
 281
 282             /* port clears */
 283             if ( data & 0x10 )
 284             {
 285                 RAM [0xF4] = 0;
 286                 RAM [0xF5] = 0;
 287             }
 288             if ( data & 0x20 )
 289             {
 290                 RAM [0xF6] = 0;
 291                 RAM [0xF7] = 0;
 292             }
 293
 294             SPC_enable_rom( this, (data & 0x80) != 0 );
 295             break;
 296         }
 297
 298         /* Ports */
 299         case 0xF4:
 300         case 0xF5:
 301         case 0xF6:
 302         case 0xF7:
 303             /* to do: handle output ports */
 304             break;
 305
 306         /* verified on SNES that these are read/write (RAM) */
 307         /*case 0xF8: */
 308         /*case 0xF9: */
 309
 310         /* Timers */
 311         case 0xFA:
 312         case 0xFB:
 313         case 0xFC: {
 314             int i = addr - 0xFA;
 315             struct Timer* t = &this->timer [i];
 316             if ( (t->period & 0xFF) != data )
 317             {
 318                 Timer_run( t, time );
 319                 this->timer[i].period = data ? data : 0x100;
 320             }
 321             break;
 322         }
 323
 324         /* Counters (cleared on write) */
 325         case 0xFD:
 326         case 0xFE:
 327         case 0xFF:
 328             /*dprintf( "Wrote to counter $%02X\n", (int) addr ); */
 329             this->timer [addr - 0xFD].counter = 0;
 330             break;
 331     }
 332 }
 333
 334 /**************** Sample generation ****************/
 335 int SPC_play( THIS, long count, int32_t* out )
 336 {
 337     int i;
 338     assert( count % 2 == 0 ); /* output is always in pairs of samples */
 339
 340     long start_time = -(count >> 1) * CLOCKS_PER_SAMPLE - EXTRA_CLOCKS;
 341
 342     /* DSP output is made on-the-fly when DSP registers are read or written */
 343     this->sample_buf = out;
 344     this->next_dsp = start_time + CLOCKS_PER_SAMPLE;
 345
 346     /* Localize timer next_tick times and run them to the present to prevent
 347        a running but ignored timer's next_tick from getting too far behind
 348        and overflowing. */
 349     for ( i = 0; i < TIMER_COUNT; i++ )
 350     {
 351         struct Timer* t = &this->timer [i];
 352         if ( t->enabled )
 353         {
 354             t->next_tick += start_time + EXTRA_CLOCKS;
 355             Timer_run( t, start_time );
 356         }
 357     }
 358
 359     /* Run from start_time to 0, pre-advancing by extra cycles from last run */
 360     this->extra_cycles = CPU_run( this, start_time + this->extra_cycles ) +
 361                          EXTRA_CLOCKS;
 362     if ( this->extra_cycles < 0 )
 363     {
 364         /*dprintf( "Unhandled instruction $%02X, pc = $%04X\n",
 365                 (int) CPU_read( r.pc ), (unsigned) r.pc ); */
 366
 367         return -1;
 368     }
 369
 370     /* Catch DSP up to present */
 371 #if 0
 372     ENTER_TIMER(cpu);
 373 #endif
 374     SPC_run_dsp( this, -EXTRA_CLOCKS );
 375 #if 0
 376     EXIT_TIMER(cpu);
 377 #endif
 378     assert( this->next_dsp == CLOCKS_PER_SAMPLE - EXTRA_CLOCKS );
 379     assert( this->sample_buf - out == count );
 380
 381     return 0;
 382 }