firmware/export/tlv320.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Christian Gmeiner
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #ifndef _TLV320_H_
  21 #define _TLV320_H_
  22
  23 #define VOLUME_MIN -730
  24 #define VOLUME_MAX  60
  25
  26 extern int tenthdb2master(int db);
  27
  28 /*** definitions ***/
  29
  30 extern void audiohw_reset(void);
  31 /**
  32  * Sets internal sample rate for DAC and ADC relative to MCLK
  33  * Selection for frequency:
  34  * Fs:        tlv:   with:
  35  * 11025: 0 = MCLK/2 MCLK/2  SCLK, LRCK: Audio Clk / 16
  36  * 22050: 0 = MCLK/2 MCLK    SCLK, LRCK: Audio Clk / 8
  37  * 44100: 1 = MCLK   MCLK    SCLK, LRCK: Audio Clk / 4 (default)
  38  * 88200: 2 = MCLK*2 MCLK    SCLK, LRCK: Audio Clk / 2
  39  */
  40 extern void audiohw_set_frequency(unsigned fsel);
  41 extern void audiohw_enable_output(bool enable);
  42 extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
  43 extern void audiohw_set_recvol(int left, int right, int type);
  44 extern void audiohw_enable_recording(bool source_mic);
  45 extern void audiohw_disable_recording(void);
  46 extern void audiohw_set_monitor(bool enable);
  47
  48 #define HEADPHONE_MUTE 0x30 /* 0110000 = -73db */
  49
  50 /* ToDo: samplerates */
  51
  52 /* registers */
  53 /* REG_LLIV: Left line input channel volume control */
  54 #define REG_LLIV        0x0
  55 #define LLIV_LRS        (1 << 8)    /* simultaneous volume/mute update  */
  56 #define LLIV_LIM        (1 << 7)    /* Left line input mute             */
  57 #define LLIV_LIV(x)     ((x) & 0x1f)/* Left line input volume control   */
  58
  59 /* REG_RLIV: Right line input channel volume control */
  60 #define REG_RLIV        0x1
  61 #define RLIV_RLS        (1 << 8)    /* simultaneous volume/mute update  */
  62 #define RLIV_RIM        (1 << 7)    /* Right line input mute            */
  63 #define RLIV_RIV(x)     ((x) & 0x1f)/* Right line input volume control  */
  64
  65 /* REG_LHV: Left Channel Headphone Volume Control */
  66 #define REG_LHV         0x2
  67 #define LHV_LRS         (1 << 8)    /* simultaneous volume/mute update */
  68 #define LHV_LZC         (1 << 7)    /* Left-channel zero-cross detect  */
  69 #define LHV_LHV(x)      ((x) & 0x7f)/* Left headphone volume control    */
  70
  71 /* REG_RHV: Right Channel Headphone Volume Control */
  72 #define REG_RHV         0x3
  73 #define RHV_LRS         (1 << 8)    /* simultaneous volume/mute update  */
  74 #define RHV_RZC         (1 << 7)    /* Right-channel zero-cross detect  */
  75 #define RHV_RHV(x)      ((x) & 0x7f)/* Right headphone volume control   */
  76
  77 /* REG_AAP: Analog Audio Path Control */
  78 #define REG_AAP         0x4
  79 #define AAP_DAC         (1 << 4)    /* DAC select           */
  80 #define AAP_BYPASS      (1 << 3)    /* bypass               */
  81 #define AAP_INSEL       (1 << 2)    /* Input select for ADC */
  82 #define AAP_MICM        (1 << 1)    /* Microphone mute      */
  83 #define AAP_MICB        (1 << 0)    /* Microphone boost     */
  84
  85 /* REG_DAP: Digital Audio Path Control */
  86 #define REG_DAP         0x5
  87 #define DAP_DACM        (1 << 3)    /* DAC soft mute                    */
  88 #define DAP_DEEMP_32    (1 << 1)    /* De-emphasis control: 32 kHz      */
  89 #define DAP_DEEMP_44    (2 << 1)    /* De-emphasis control: 44.1 kHz    */
  90 #define DAP_DEEMP_48    (3 << 1)    /* De-emphasis control: 48 kHz      */
  91 #define DAP_ADCHP       (1 << 0)    /* ADC high-pass filter             */
  92
  93 /* REG_PC: Power Down Control */
  94 #define REG_PC          0x6
  95 #define PC_OFF          (1 << 7)    /* Device power     */
  96 #define PC_CLK          (1 << 6)    /* Clock            */
  97 #define PC_OSC          (1 << 5)    /* Oscillator       */
  98 #define PC_OUT          (1 << 4)    /* Outputs          */
  99 #define PC_DAC          (1 << 3)    /* DAC              */
 100 #define PC_ADC          (1 << 2)    /* ADC              */
 101 #define PC_MIC          (1 << 1)    /* Microphone input */
 102 #define PC_LINE         (1 << 0)    /* Line input       */
 103
 104 /* REG_DAIF: Digital Audio Interface Format */
 105 #define REG_DAIF        0x7
 106 #define DAIF_MS         (1 << 6)    /* Master/slave mode                        */
 107 #define DAIF_LRSWAP     (1 << 5)    /* DAC left/right swap                      */
 108 #define DAIF_LRP        (1 << 4)    /* DAC left/right phase                     */
 109 #define DAIF_IWL_16     (0 << 2)    /* Input bit length: 16 bit                 */
 110 #define DAIF_IWL_20     (1 << 2)    /* Input bit length: 20 bit                 */
 111 #define DAIF_IWL_24     (2 << 2)    /* Input bit length: 24 bit                 */
 112 #define DAIF_IWL_32     (3 << 2)    /* Input bit length: 32 bit                 */
 113 #define DAIF_FOR_DSP    (3 << 0)    /* Data format: DSP                         */
 114 #define DAIF_FOR_I2S    (2 << 0)    /* Data format: I2S                         */
 115 #define DAIF_FOR_MSBL   (1 << 0)    /* Data format: MSB first, left aligned     */
 116 #define DAIF_FOR_MSBR   (0 << 0)    /* Data format: MSB first, right aligned    */
 117
 118 /* REG_SRC: Sample Rate Control */
 119 #define REG_SRC         0x8
 120 #define SRC_CLKIN       (1 << 6)    /* Clock input divider                          */
 121 #define SRC_CLKOUT      (1 << 7)    /* Clock output divider                         */
 122 /*#define SRC_SR        ()*/
 123 #define SRC_BOSR        (1 << 1)    /* Base oversampling rate, depends on SRC_USB   */
 124 #define SRC_USB         (1 << 0)    /* Clock mode select                            */
 125
 126 /* REG_DIA: Digital Interface Activation */
 127 #define REG_DIA         0x9
 128 #define DIA_ACT         (1 << 0)    /* Activate interface */
 129
 130 /* REG_RR: Reset Register */
 131 #define REG_RR          0xf
 132 #define RR_RESET        0           /* Reset */
 133
 134 #endif /*_TLV320_H_*/