firmware/export/uda1380.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #ifndef _UDA1380_H
  21 #define _UDA1380_H
  22
  23 /* volume/balance/treble/bass interdependency */
  24 #define VOLUME_MIN -840
  25 #define VOLUME_MAX  0
  26
  27 extern int tenthdb2master(int db);
  28 extern int tenthdb2mixer(int db);
  29
  30 extern void audiohw_set_master_vol(int vol_l, int vol_r);
  31 extern void audiohw_set_mixer_vol(int channel1, int channel2);
  32 extern void audiohw_set_bass(int value);
  33 extern void audiohw_set_treble(int value);
  34
  35 /**
  36  * Sets frequency settings for DAC and ADC relative to MCLK
  37  *
  38  * Selection for frequency ranges:
  39  *  Fs:        range:       with:
  40  *  11025: 0 = 6.25 to 12.5 SCLK, LRCK: Audio Clk / 16
  41  *  22050: 1 = 12.5 to 25   SCLK, LRCK: Audio Clk / 8
  42  *  44100: 2 = 25   to 50   SCLK, LRCK: Audio Clk / 4 (default)
  43  *  88200: 3 = 50   to 100  SCLK, LRCK: Audio Clk / 2
  44  */
  45 extern void audiohw_set_frequency(unsigned fsel);
  46
  47 #define UDA1380_ADDR        0x30
  48
  49 /* REG_0: Misc settings */
  50 #define REG_0               0x00
  51 #define EN_ADC              (1 << 11)    /* Enable ADC                     */
  52 #define EN_DEC              (1 << 10)    /* Enable Decimator               */
  53 #define EN_DAC              (1 << 9)     /* Enable DAC                     */
  54 #define EN_INT              (1 << 8)     /* Enable Interpolator            */
  55 #define ADC_CLK             (1 << 5)     /* ADC_CLK: WSPLL (1) SYSCLK (0)  */
  56 #define DAC_CLK             (1 << 4)     /* DAC_CLK: WSPLL (1) SYSCLK (0)  */
  57
  58 /* SYSCLK freqency select */
  59 #define SYSCLK_256FS        (0 << 2)
  60 #define SYSCLK_384FS        (1 << 2)
  61 #define SYSCLK_512FS        (2 << 2)
  62 #define SYSCLK_768FS        (3 << 2)
  63
  64 /* WSPLL Input frequency range (kHz) */
  65 #define WSPLL_625_125       (0 << 0)     /* 6.25 - 12.5      */
  66 #define WSPLL_125_25        (1 << 0)     /* 12.5 - 25        */
  67 #define WSPLL_25_50         (2 << 0)     /* 25   - 50        */
  68 #define WSPLL_50_100        (3 << 0)     /* 50   - 100       */
  69
  70
  71 /* REG_I2S: I2S settings */
  72 #define REG_I2S                 0x01
  73 #define I2S_IFMT_IIS        (0 << 8)
  74 #define I2S_IFMT_LSB16      (1 << 8)
  75 #define I2S_IFMT_LSB18      (2 << 8)
  76 #define I2S_IFMT_LSB20      (3 << 8)
  77 #define I2S_IFMT_MSB        (5 << 8)
  78 #define I2S_OFMT_IIS        (0 << 0)
  79 #define I2S_OFMT_LSB16      (1 << 0)
  80 #define I2S_OFMT_LSB18      (2 << 0)
  81 #define I2S_OFMT_LSB20      (3 << 0)
  82 #define I2S_OFMT_LSB24      (4 << 0)
  83 #define I2S_OFMT_MSB        (5 << 0)
  84 #define I2S_MODE_MASTER     (1 << 4)
  85
  86 /* REG_PWR: Power control */
  87 #define REG_PWR             0x02
  88 #define PON_PLL             (1 << 15)   /* Power-on WSPLL                     */
  89 #define PON_HP              (1 << 13)   /* Power-on Headphone driver          */
  90 #define PON_DAC             (1 << 10)   /* Power-on DAC                       */
  91 #define PON_BIAS            (1 << 8)    /* Power-on BIAS for ADC, AVC, FSDAC  */
  92 #define EN_AVC              (1 << 7)    /* Enable analog mixer                */
  93 #define PON_AVC             (1 << 6)    /* Power-on analog mixer              */
  94 #define PON_LNA             (1 << 4)    /* Power-on LNA & SDC                 */
  95 #define PON_PGAL            (1 << 3)    /* Power-on PGA left                  */
  96 #define PON_ADCL            (1 << 2)    /* Power-on ADC left                  */
  97 #define PON_PGAR            (1 << 1)    /* Power-on PGA right                 */
  98 #define PON_ADCR            (1 << 0)    /* Power-on ADC right                 */
  99
 100
 101 /* REG_AMIX: Analog mixer */
 102 #define REG_AMIX            0x03
 103 #define AMIX_LEFT(x)        (((x) & 0x3f) << 8)
 104 #define AMIX_RIGHT(x)       (((x) & 0x3f) << 0)
 105
 106 /* REG_HP: Headphone amp */
 107 #define REG_HP              0x04
 108
 109 /* REG_MV: Master Volume control */
 110 #define REG_MASTER_VOL      0x10
 111
 112 #define MASTER_VOL_RIGHT(x) (((x) & 0xff) << 8)
 113 #define MASTER_VOL_LEFT(x)  (((x) & 0xff) << 0)
 114
 115 /* REG_MIX: Mixer volume control */
 116 /* Channel 1 is from digital data from I2S */
 117 /* Channel 2 is from decimation filter */
 118
 119 #define REG_MIX_VOL         0x11
 120 #define MIX_VOL_CH_1(x)     (((x) & 0xff) << 0)
 121 #define MIX_VOL_CH_2(x)     (((x) & 0xff) << 8)
 122
 123 /* REG_EQ: Bass boost and tremble */
 124 #define REG_EQ              0x12
 125 #define EQ_MODE_FLAT        (0 << 14)
 126 #define EQ_MODE_MIN         (1 << 14)
 127 #define EQ_MODE_MAX         (3 << 14)
 128 #define BASSL(x)            (((x) & 0x1E) << 7)
 129 #define BASSR(x)            (((x) & 0x1E) >> 1)
 130 #define TREBLEL(x)          (((x) & 0x6) << 11)
 131 #define TREBLER(x)          (((x) & 0x6) << 3)
 132 #define BASS_MASK           0x0F0F
 133 #define TREBLE_MASK         0x3030
 134
 135 /* REG_MUTE: Master Mute, silence detector and oversampling */
 136 #define REG_MUTE            0x13
 137 #define MUTE_MASTER         (1 << 14)      /* Master Mute (soft)       */
 138 #define MUTE_CH2            (1 << 11)      /* Channel 2 mute           */
 139 #define MUTE_CH1            (1 << 3)       /* Channel 1 mute           */
 140 #define DE_EMPHASIS_NONE    (0 << 8)       /* no de-emphasis           */
 141 #define DE_EMPHASIS_32kHz   (1 << 8)       /* 32 kHz                   */
 142 #define DE_EMPHASIS_44kHz   (2 << 8)       /* 44.1 kHz                 */
 143 #define DE_EMPHASIS_48kHz   (3 << 8)       /* 48 kHz                   */
 144 #define DE_EMPHASIS_96kHz   (4 << 8)       /* 96 kHz                   */
 145
 146 /* REG_MIX_CTL: Mixer, silence detector and oversampling settings */
 147 #define REG_MIX_CTL         0x14
 148 #define DAC_INVERT          (1 << 15)      /* invert DAC polarity      */
 149 #define MIX_CTL_SEL_NS      (1 << 14)      /* 0 = 3rd, 1 = 5th order   */
 150 #define MIX_CTL_MIX_POS     (1 << 13)      /* MIX MODE bit MIX POS     */
 151 #define MIX_CTL_MIX         (1 << 12)      /* MIX MODE bit MIX         */
 152 #define MIX_MODE(x)         (((x) & 0x3) << 12) /* Mixer mode: See table 48 */
 153 #define SILENCE_MODE        (1 << 7)       /* force silence output     */
 154 #define SILENCE_DET_ON      (1 << 6)       /* enable silence detection */
 155 #define SILENCE_DET(x)      (((x) & 0x3) << 4) /* silence detection value  */
 156 #define SILENCE_DET_3200    (0 << 4)       /* 3200 samples             */
 157 #define SILENCE_DET_4800    (1 << 4)       /* 4800 samples             */
 158 #define SILENCE_DET_9600    (2 << 4)       /* 9600 samples             */
 159 #define SILENCE_DET_19200   (3 << 4)       /* 19200 samples            */
 160 #define OVERSAMPLE_MODE(x)  (((x) & 0x3) << 0) /* oversampling mode        */
 161
 162 /* REG_DEC_VOL: Decimator (ADC) volume control */
 163 #define REG_DEC_VOL         0x20
 164 #define DEC_VOLL(x)         (((x) & 0xff) << 8)
 165 #define DEC_VOLR(x)         (((x) & 0xff) << 0)
 166
 167 /* REG_PGA: PGA settings and mute */
 168 #define REG_PGA             0x21
 169 #define MUTE_ADC            (1 << 15)               /* Mute ADC */
 170 #define PGA_GAINR(x)        (((x) & 0xF) << 8)
 171 #define PGA_GAINL(x)        (((x) & 0xF) << 0)
 172 #define PGA_GAIN_MASK       0x0F0F
 173
 174 /* REG_ADC: */
 175 #define REG_ADC             0x22
 176 #define ADC_INVERT          (1 << 12)       /* invert ADC polarity      */
 177 #define VGA_GAIN(x)         (((x) & 0xF) << 8)
 178 #define VGA_GAIN_MASK       0x0F00
 179 #define SEL_LNA             (1 << 3)
 180 #define SEL_MIC             (1 << 2)
 181 #define SKIP_DCFIL          (1 << 1)
 182 #define EN_DCFIL            (1 << 0)
 183
 184 /* REG_AGC: Attack / Gain */
 185 #define REG_AGC             0x23
 186
 187 #endif /* _UDA_1380_H */