RF24.cpp

   1 /*
   2  Copyright (C) 2011 James Coliz, Jr. <maniacbug@ymail.com>
   3
   4  This program is free software; you can redistribute it and/or
   5  modify it under the terms of the GNU General Public License
   6  version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #if ARDUINO < 100
  10 #include <WProgram.h>
  11 #else
  12 #include <Arduino.h>
  13 #endif
  14
  15 #include <SPI.h>
  16 #include "nRF24L01.h"
  17 #include "RF24.h"
  18
  19 #undef SERIAL_DEBUG
  20 #ifdef SERIAL_DEBUG
  21 #define IF_SERIAL_DEBUG(x) ({x;})
  22 #else
  23 #define IF_SERIAL_DEBUG(x)
  24 #endif
  25
  26 // Avoid spurious warnings
  27 #if ! defined( NATIVE ) && defined( ARDUINO )
  28 #undef PROGMEM
  29 #define PROGMEM __attribute__(( section(".progmem.data") ))
  30 #undef PSTR
  31 #define PSTR(s) (__extension__({static prog_char __c[] PROGMEM = (s); &__c[0];}))
  32 #endif
  33
  34 #ifdef ARDUINO
  35 #define PRIPSTR "%S"
  36 #else
  37 #define PRIPSTR "%s"
  38 #endif
  39
  40 /****************************************************************************/
  41
  42 void RF24::csn(int mode)
  43 {
  44   // Minimum ideal SPI bus speed is 2x data rate
  45   // If we assume 2Mbs data rate and 16Mhz clock, a
  46   // divider of 4 is the minimum we want.
  47   // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
  48 #ifdef ARDUINO
  49   SPI.setBitOrder(MSBFIRST);
  50   SPI.setDataMode(SPI_MODE0);
  51   SPI.setClockDivider(SPI_CLOCK_DIV4);
  52 #endif
  53   digitalWrite(csn_pin,mode);
  54 }
  55
  56 /****************************************************************************/
  57
  58 void RF24::ce(int level)
  59 {
  60   digitalWrite(ce_pin,level);
  61 }
  62
  63 /****************************************************************************/
  64
  65 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
  66 {
  67   uint8_t status;
  68
  69   csn(LOW);
  70   status = SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
  71   while ( len-- )
  72     *buf++ = SPI.transfer(0xff);
  73
  74   csn(HIGH);
  75
  76   return status;
  77 }
  78
  79 /****************************************************************************/
  80
  81 uint8_t RF24::read_register(uint8_t reg)
  82 {
  83   csn(LOW);
  84   SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
  85   uint8_t result = SPI.transfer(0xff);
  86
  87   csn(HIGH);
  88   return result;
  89 }
  90
  91 /****************************************************************************/
  92
  93 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
  94 {
  95   uint8_t status;
  96
  97   csn(LOW);
  98   status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
  99   while ( len-- )
 100     SPI.transfer(*buf++);
 101
 102   csn(HIGH);
 103
 104   return status;
 105 }
 106
 107 /****************************************************************************/
 108
 109 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
 110 {
 111   uint8_t status;
 112
 113   IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
 114
 115   csn(LOW);
 116   status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
 117   SPI.transfer(value);
 118   csn(HIGH);
 119
 120   return status;
 121 }
 122
 123 /****************************************************************************/
 124
 125 uint8_t RF24::write_payload(const void* buf, uint8_t len)
 126 {
 127   uint8_t status;
 128
 129   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
 130
 131   uint8_t data_len = min(len,payload_size);
 132   uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
 133
 134   //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
 135
 136   csn(LOW);
 137   status = SPI.transfer( W_TX_PAYLOAD );
 138   while ( data_len-- )
 139     SPI.transfer(*current++);
 140   while ( blank_len-- )
 141     SPI.transfer(0);
 142   csn(HIGH);
 143
 144   return status;
 145 }
 146
 147 /****************************************************************************/
 148
 149 uint8_t RF24::read_payload(void* buf, uint8_t len)
 150 {
 151   uint8_t status;
 152   uint8_t* current = reinterpret_cast<uint8_t*>(buf);
 153
 154   uint8_t data_len = min(len,payload_size);
 155   uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
 156
 157   //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
 158
 159   csn(LOW);
 160   status = SPI.transfer( R_RX_PAYLOAD );
 161   while ( data_len-- )
 162     *current++ = SPI.transfer(0xff);
 163   while ( blank_len-- )
 164     SPI.transfer(0xff);
 165   csn(HIGH);
 166
 167   return status;
 168 }
 169
 170 /****************************************************************************/
 171
 172 uint8_t RF24::flush_rx(void)
 173 {
 174   uint8_t status;
 175
 176   csn(LOW);
 177   status = SPI.transfer( FLUSH_RX );
 178   csn(HIGH);
 179
 180   return status;
 181 }
 182
 183 /****************************************************************************/
 184
 185 uint8_t RF24::flush_tx(void)
 186 {
 187   uint8_t status;
 188
 189   csn(LOW);
 190   status = SPI.transfer( FLUSH_TX );
 191   csn(HIGH);
 192
 193   return status;
 194 }
 195
 196 /****************************************************************************/
 197
 198 uint8_t RF24::get_status(void)
 199 {
 200   uint8_t status;
 201
 202   csn(LOW);
 203   status = SPI.transfer( NOP );
 204   csn(HIGH);
 205
 206   return status;
 207 }
 208
 209 /****************************************************************************/
 210
 211 void RF24::print_status(uint8_t status)
 212 {
 213   printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
 214            status,
 215            (status & _BV(RX_DR))?1:0,
 216            (status & _BV(TX_DS))?1:0,
 217            (status & _BV(MAX_RT))?1:0,
 218            ((status >> RX_P_NO) & B111),
 219            (status & _BV(TX_FULL))?1:0
 220           );
 221 }
 222
 223 /****************************************************************************/
 224
 225 void RF24::print_observe_tx(uint8_t value)
 226 {
 227   printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
 228            value,
 229            (value >> PLOS_CNT) & B1111,
 230            (value >> ARC_CNT) & B1111
 231           );
 232 }
 233
 234 /****************************************************************************/
 235
 236 void RF24::print_byte_register(prog_char* name, uint8_t reg, uint8_t qty)
 237 {
 238   char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
 239   printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
 240   while (qty--)
 241     printf_P(PSTR(" 0x%02x"),read_register(reg++));
 242   printf_P(PSTR("\r\n"));
 243 }
 244
 245 /****************************************************************************/
 246
 247 void RF24::print_address_register(prog_char* name, uint8_t reg, uint8_t qty)
 248 {
 249   char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
 250   printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
 251
 252   while (qty--)
 253   {
 254     uint8_t buffer[5];
 255     read_register(reg++,buffer,sizeof buffer);
 256
 257     printf_P(PSTR(" 0x"));
 258     uint8_t* bufptr = buffer + sizeof buffer;
 259     while( --bufptr >= buffer )
 260       printf_P(PSTR("%02x"),*bufptr);
 261   }
 262
 263   printf_P(PSTR("\r\n"));
 264 }
 265
 266 /****************************************************************************/
 267
 268 RF24::RF24(uint8_t _cepin, uint8_t _cspin):
 269   ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false),
 270   payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
 271   pipe0_reading_address(0)
 272 {
 273 }
 274
 275 /****************************************************************************/
 276
 277 void RF24::setChannel(uint8_t channel)
 278 {
 279   // TODO: This method could take advantage of the 'wide_band' calculation
 280   // done in setChannel() to require certain channel spacing.
 281
 282   const uint8_t max_channel = 127;
 283   write_register(RF_CH,min(channel,max_channel));
 284 }
 285
 286 /****************************************************************************/
 287
 288 void RF24::setPayloadSize(uint8_t size)
 289 {
 290   const uint8_t max_payload_size = 32;
 291   payload_size = min(size,max_payload_size);
 292 }
 293
 294 /****************************************************************************/
 295
 296 uint8_t RF24::getPayloadSize(void)
 297 {
 298   return payload_size;
 299 }
 300
 301 /****************************************************************************/
 302
 303 void RF24::printDetails(void)
 304 {
 305   print_status(get_status());
 306
 307   print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
 308   print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
 309   print_address_register(PSTR("TX_ADDR"),TX_ADDR);
 310
 311   print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
 312   print_byte_register(PSTR("EN_AA"),EN_AA);
 313   print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
 314   print_byte_register(PSTR("RF_CH"),RF_CH);
 315   print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
 316   print_byte_register(PSTR("CONFIG"),CONFIG);
 317   print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
 318
 319   const char * rf24_datarate_e_str[] = { "1MBPS", "2MBPS", "250KBPS" };
 320   const char * rf24_model_e_str[] = { "nRF24L01", "nRF24L01+" } ;
 321   const char * rf24_crclength_e_str[] = { "Disabled", "8 bits", "16 bits" } ;
 322   const char * rf24_pa_dbm_e_str[] = { "PA_MIN", "PA_LOW", "LA_MED", "PA_HIGH"} ;
 323
 324   printf_P(PSTR("Data Rate\t = %s\r\n"),rf24_datarate_e_str[getDataRate()]);
 325   printf_P(PSTR("Model\t\t = %s\r\n"),rf24_model_e_str[isPVariant()]);
 326   printf_P(PSTR("CRC Length\t = %s\r\n"),rf24_crclength_e_str[getCRCLength()]);
 327   printf_P(PSTR("PA Power\t = %s\r\n"),rf24_pa_dbm_e_str[getPALevel()]);
 328 }
 329
 330 /****************************************************************************/
 331
 332 void RF24::begin(void)
 333 {
 334   // Initialize pins
 335   pinMode(ce_pin,OUTPUT);
 336   pinMode(csn_pin,OUTPUT);
 337
 338   // Initialize SPI bus
 339   SPI.begin();
 340
 341   ce(LOW);
 342   csn(HIGH);
 343
 344   // Must allow the radio time to settle else configuration bits will not necessarily stick.
 345   // This is actually only required following power up but some settling time also appears to
 346   // be required after resets too. For full coverage, we'll always assume the worst.
 347   // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
 348   // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
 349   // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
 350   delay( 5 ) ;
 351
 352   // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
 353   // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
 354   // sizes must never be used. See documentation for a more complete explanation.
 355   write_register(SETUP_RETR,(B0100 << ARD) | (B1111 << ARC));
 356
 357   // Restore our default PA level
 358   setPALevel( RF24_PA_MAX ) ;
 359
 360   // Determine if this is a p or non-p RF24 module and then
 361   // reset our data rate back to default value. This works
 362   // because a non-P variant won't allow the data rate to
 363   // be set to 250Kbps.
 364   if( setDataRate( RF24_250KBPS ) )
 365   {
 366     p_variant = true ;
 367   }
 368
 369   // Then set the data rate to the slowest (and most reliable) speed supported by all
 370   // hardware.
 371   setDataRate( RF24_1MBPS ) ;
 372
 373   // Initialize CRC and request 2-byte (16bit) CRC
 374   setCRCLength( RF24_CRC_16 ) ;
 375
 376   // Disable dynamic payloads, to match dynamic_payloads_enabled setting
 377   write_register(DYNPD,0);
 378
 379   // Reset current status
 380   // Notice reset and flush is the last thing we do
 381   write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 382
 383   // Set up default configuration.  Callers can always change it later.
 384   // This channel should be universally safe and not bleed over into adjacent
 385   // spectrum.
 386   setChannel(76);
 387
 388   // Flush buffers
 389   flush_rx();
 390   flush_tx();
 391 }
 392
 393 /****************************************************************************/
 394
 395 void RF24::startListening(void)
 396 {
 397   write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
 398   write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 399
 400   // Restore the pipe0 adddress, if exists
 401   if (pipe0_reading_address)
 402     write_register(RX_ADDR_P0, reinterpret_cast<const uint8_t*>(&pipe0_reading_address), 5);
 403
 404   // Flush buffers
 405   flush_rx();
 406   flush_tx();
 407
 408   // Go!
 409   ce(HIGH);
 410
 411   // wait for the radio to come up (130us actually only needed)
 412   delayMicroseconds(130);
 413 }
 414
 415 /****************************************************************************/
 416
 417 void RF24::stopListening(void)
 418 {
 419   ce(LOW);
 420   flush_tx();
 421   flush_rx();
 422 }
 423
 424 /****************************************************************************/
 425
 426 void RF24::powerDown(void)
 427 {
 428   write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
 429 }
 430
 431 /****************************************************************************/
 432
 433 void RF24::powerUp(void)
 434 {
 435   write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
 436 }
 437
 438 /******************************************************************/
 439
 440 bool RF24::write( const void* buf, uint8_t len )
 441 {
 442   bool result = false;
 443
 444   // Begin the write
 445   startWrite(buf,len);
 446
 447   // ------------
 448   // At this point we could return from a non-blocking write, and then call
 449   // the rest after an interrupt
 450
 451   // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
 452   // or MAX_RT (maximum retries, transmission failed).  Also, we'll timeout in case the radio
 453   // is flaky and we get neither.
 454
 455   // IN the end, the send should be blocking.  It comes back in 60ms worst case, or much faster
 456   // if I tighted up the retry logic.  (Default settings will be 1500us.
 457   // Monitor the send
 458   uint8_t observe_tx;
 459   uint8_t status;
 460   uint32_t sent_at = millis();
 461   const uint32_t timeout = 500; //ms to wait for timeout
 462   do
 463   {
 464     status = read_register(OBSERVE_TX,&observe_tx,1);
 465     IF_SERIAL_DEBUG(Serial.print(observe_tx,HEX));
 466   }
 467   while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) );
 468
 469   // The part above is what you could recreate with your own interrupt handler,
 470   // and then call this when you got an interrupt
 471   // ------------
 472
 473   // Call this when you get an interrupt
 474   // The status tells us three things
 475   // * The send was successful (TX_DS)
 476   // * The send failed, too many retries (MAX_RT)
 477   // * There is an ack packet waiting (RX_DR)
 478   bool tx_ok, tx_fail;
 479   whatHappened(tx_ok,tx_fail,ack_payload_available);
 480
 481   //printf("%u%u%u\r\n",tx_ok,tx_fail,ack_payload_available);
 482
 483   result = tx_ok;
 484   IF_SERIAL_DEBUG(Serial.print(result?"...OK.":"...Failed"));
 485
 486   // Handle the ack packet
 487   if ( ack_payload_available )
 488   {
 489     ack_payload_length = getDynamicPayloadSize();
 490     IF_SERIAL_DEBUG(Serial.print("[AckPacket]/"));
 491     IF_SERIAL_DEBUG(Serial.println(ack_payload_length,DEC));
 492   }
 493
 494   // Yay, we are done.
 495
 496   // Power down
 497   powerDown();
 498
 499   // Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
 500   flush_tx();
 501
 502   return result;
 503 }
 504 /****************************************************************************/
 505
 506 void RF24::startWrite( const void* buf, uint8_t len )
 507 {
 508   // Transmitter power-up
 509   write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
 510   delay(2);
 511
 512   // Send the payload
 513   write_payload( buf, len );
 514
 515   // Allons!
 516   ce(HIGH);
 517   delayMicroseconds(15);
 518   delay(2);
 519   ce(LOW);
 520 }
 521
 522 /****************************************************************************/
 523
 524 uint8_t RF24::getDynamicPayloadSize(void)
 525 {
 526   uint8_t result = 0;
 527
 528   csn(LOW);
 529   SPI.transfer( R_RX_PL_WID );
 530   result = SPI.transfer(0xff);
 531   csn(HIGH);
 532
 533   return result;
 534 }
 535
 536 /****************************************************************************/
 537
 538 bool RF24::available(void)
 539 {
 540   return available(NULL);
 541 }
 542
 543 /****************************************************************************/
 544
 545 bool RF24::available(uint8_t* pipe_num)
 546 {
 547   uint8_t status = get_status();
 548
 549   // Too noisy, enable if you really want lots o data!!
 550   //IF_SERIAL_DEBUG(print_status(status));
 551
 552   bool result = ( status & _BV(RX_DR) );
 553
 554   if (result)
 555   {
 556     // If the caller wants the pipe number, include that
 557     if ( pipe_num )
 558       *pipe_num = ( status >> RX_P_NO ) & B111;
 559
 560     // Clear the status bit
 561
 562     // ??? Should this REALLY be cleared now?  Or wait until we
 563     // actually READ the payload?
 564
 565     write_register(STATUS,_BV(RX_DR) );
 566
 567     // Handle ack payload receipt
 568     if ( status & _BV(TX_DS) )
 569     {
 570       write_register(STATUS,_BV(TX_DS));
 571     }
 572   }
 573
 574   return result;
 575 }
 576
 577 /****************************************************************************/
 578
 579 bool RF24::read( void* buf, uint8_t len )
 580 {
 581   // Fetch the payload
 582   read_payload( buf, len );
 583
 584   // was this the last of the data available?
 585   return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
 586 }
 587
 588 /****************************************************************************/
 589
 590 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
 591 {
 592   // Read the status & reset the status in one easy call
 593   // Or is that such a good idea?
 594   uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 595
 596   // Report to the user what happened
 597   tx_ok = status & _BV(TX_DS);
 598   tx_fail = status & _BV(MAX_RT);
 599   rx_ready = status & _BV(RX_DR);
 600 }
 601
 602 /****************************************************************************/
 603
 604 void RF24::openWritingPipe(uint64_t value)
 605 {
 606   // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
 607   // expects it LSB first too, so we're good.
 608
 609   write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), 5);
 610   write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), 5);
 611
 612   const uint8_t max_payload_size = 32;
 613   write_register(RX_PW_P0,min(payload_size,max_payload_size));
 614 }
 615
 616 /****************************************************************************/
 617
 618 void RF24::openReadingPipe(uint8_t child, uint64_t address)
 619 {
 620   const uint8_t child_pipe[] =
 621   {
 622     RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
 623   };
 624   const uint8_t child_payload_size[] =
 625   {
 626     RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
 627   };
 628   const uint8_t child_pipe_enable[] =
 629   {
 630     ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
 631   };
 632
 633   // If this is pipe 0, cache the address.  This is needed because
 634   // openWritingPipe() will overwrite the pipe 0 address, so
 635   // startListening() will have to restore it.
 636   if (child == 0)
 637     pipe0_reading_address = address;
 638
 639   if (child <= 6)
 640   {
 641     // For pipes 2-5, only write the LSB
 642     if ( child < 2 )
 643       write_register(child_pipe[child], reinterpret_cast<const uint8_t*>(&address), 5);
 644     else
 645       write_register(child_pipe[child], reinterpret_cast<const uint8_t*>(&address), 1);
 646
 647     write_register(child_payload_size[child],payload_size);
 648
 649     // Note it would be more efficient to set all of the bits for all open
 650     // pipes at once.  However, I thought it would make the calling code
 651     // more simple to do it this way.
 652     write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(child_pipe_enable[child]));
 653   }
 654 }
 655
 656 /****************************************************************************/
 657
 658 void RF24::toggle_features(void)
 659 {
 660   csn(LOW);
 661   SPI.transfer( ACTIVATE );
 662   SPI.transfer( 0x73 );
 663   csn(HIGH);
 664 }
 665
 666 /****************************************************************************/
 667
 668 void RF24::enableDynamicPayloads(void)
 669 {
 670   // Enable dynamic payload throughout the system
 671   write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
 672
 673   // If it didn't work, the features are not enabled
 674   if ( ! read_register(FEATURE) )
 675   {
 676     // So enable them and try again
 677     toggle_features();
 678     write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
 679   }
 680
 681   IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
 682
 683   // Enable dynamic payload on all pipes
 684   //
 685   // Not sure the use case of only having dynamic payload on certain
 686   // pipes, so the library does not support it.
 687   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
 688
 689   dynamic_payloads_enabled = true;
 690 }
 691
 692 /****************************************************************************/
 693
 694 void RF24::enableAckPayload(void)
 695 {
 696   //
 697   // enable ack payload and dynamic payload features
 698   //
 699
 700   write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
 701
 702   // If it didn't work, the features are not enabled
 703   if ( ! read_register(FEATURE) )
 704   {
 705     // So enable them and try again
 706     toggle_features();
 707     write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
 708   }
 709
 710   IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
 711
 712   //
 713   // Enable dynamic payload on pipes 0 & 1
 714   //
 715
 716   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
 717 }
 718
 719 /****************************************************************************/
 720
 721 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
 722 {
 723   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
 724
 725   csn(LOW);
 726   SPI.transfer( W_ACK_PAYLOAD | ( pipe & B111 ) );
 727   const uint8_t max_payload_size = 32;
 728   uint8_t data_len = min(len,max_payload_size);
 729   while ( data_len-- )
 730     SPI.transfer(*current++);
 731
 732   csn(HIGH);
 733 }
 734
 735 /****************************************************************************/
 736
 737 bool RF24::isAckPayloadAvailable(void)
 738 {
 739   bool result = ack_payload_available;
 740   ack_payload_available = false;
 741   return result;
 742 }
 743
 744 /****************************************************************************/
 745
 746 bool RF24::isPVariant(void)
 747 {
 748   return p_variant ;
 749 }
 750
 751 /****************************************************************************/
 752
 753 void RF24::setAutoAck(bool enable)
 754 {
 755   if ( enable )
 756     write_register(EN_AA, B111111);
 757   else
 758     write_register(EN_AA, 0);
 759 }
 760
 761 /****************************************************************************/
 762
 763 void RF24::setAutoAck( uint8_t pipe, bool enable )
 764 {
 765   if ( pipe <= 6 )
 766   {
 767     uint8_t en_aa = read_register( EN_AA ) ;
 768     if( enable )
 769     {
 770       en_aa |= _BV(pipe) ;
 771     }
 772     else
 773     {
 774       en_aa &= ~_BV(pipe) ;
 775     }
 776     write_register( EN_AA, en_aa ) ;
 777   }
 778 }
 779
 780 /****************************************************************************/
 781
 782 bool RF24::testCarrier(void)
 783 {
 784   return ( read_register(CD) & 1 );
 785 }
 786
 787 /****************************************************************************/
 788
 789 bool RF24::testRPD(void)
 790 {
 791   return ( read_register(RPD) & 1 ) ;
 792 }
 793
 794 /****************************************************************************/
 795
 796 void RF24::setPALevel(rf24_pa_dbm_e level)
 797 {
 798   uint8_t setup = read_register(RF_SETUP) ;
 799   setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 800
 801   switch( level )
 802   {
 803   case RF24_PA_MAX:
 804     setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 805     break ;
 806
 807   case RF24_PA_HIGH:
 808     setup |= _BV(RF_PWR_HIGH) ;
 809     break ;
 810
 811   case RF24_PA_LOW:
 812     setup |= _BV(RF_PWR_LOW) ;
 813     break ;
 814
 815   case RF24_PA_MIN:
 816     break ;
 817
 818   case RF24_PA_ERROR:
 819     // On error, go to maximum PA
 820     setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 821     break ;
 822   }
 823
 824   write_register( RF_SETUP, setup ) ;
 825 }
 826
 827 /****************************************************************************/
 828
 829 rf24_pa_dbm_e RF24::getPALevel(void)
 830 {
 831   rf24_pa_dbm_e result = RF24_PA_ERROR ;
 832   uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 833
 834   switch( power )
 835   {
 836   case (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)):
 837     result = RF24_PA_MAX ;
 838     break ;
 839
 840   case _BV(RF_PWR_HIGH):
 841     result = RF24_PA_HIGH ;
 842     break ;
 843
 844   case _BV(RF_PWR_LOW):
 845     result = RF24_PA_LOW ;
 846     break ;
 847
 848   default:
 849     result = RF24_PA_MIN ;
 850     break ;
 851   }
 852
 853   return result ;
 854 }
 855
 856 /****************************************************************************/
 857
 858 bool RF24::setDataRate(rf24_datarate_e speed)
 859 {
 860   bool result = false;
 861   uint8_t setup = read_register(RF_SETUP) ;
 862
 863   // HIGH and LOW '00' is 1Mbs - our default
 864   wide_band = false ;
 865   setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
 866   if( speed == RF24_250KBPS )
 867   {
 868     // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
 869     // Making it '10'.
 870     wide_band = false ;
 871     setup |= _BV( RF_DR_LOW ) ;
 872   }
 873   else
 874   {
 875     // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
 876     // Making it '01'
 877     if ( speed == RF24_2MBPS )
 878     {
 879       wide_band = true ;
 880       setup |= _BV(RF_DR_HIGH);
 881     }
 882     else
 883     {
 884       // 1Mbs
 885       wide_band = false ;
 886     }
 887   }
 888   write_register(RF_SETUP,setup);
 889
 890   // Verify our result
 891   if ( read_register(RF_SETUP) == setup )
 892   {
 893     result = true;
 894   }
 895   else
 896   {
 897     wide_band = false;
 898   }
 899
 900   return result;
 901 }
 902
 903 /****************************************************************************/
 904
 905 rf24_datarate_e RF24::getDataRate( void )
 906 {
 907   rf24_datarate_e result ;
 908   uint8_t setup = read_register(RF_SETUP) ;
 909
 910   // Order matters in our case below
 911   switch( setup & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) )
 912   {
 913   case _BV(RF_DR_LOW):
 914     // '10' = 250KBPS
 915     result = RF24_250KBPS ;
 916     break ;
 917
 918   case _BV(RF_DR_HIGH):
 919     // '01' = 2MBPS
 920     result = RF24_2MBPS ;
 921     break ;
 922
 923   default:
 924     // '00' = 1MBPS
 925     result = RF24_1MBPS ;
 926     break ;
 927   }
 928
 929   return result ;
 930 }
 931
 932 /****************************************************************************/
 933
 934 void RF24::setCRCLength(rf24_crclength_e length)
 935 {
 936   uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
 937
 938   switch (length)
 939   {
 940     case RF24_CRC_DISABLED:
 941       break;
 942
 943     case RF24_CRC_8:
 944       config |= _BV(EN_CRC);
 945       break;
 946
 947     case RF24_CRC_16:
 948     default:
 949       config |= _BV(EN_CRC);
 950       config |= _BV( CRCO );
 951       break;
 952   }
 953
 954   write_register( CONFIG, config ) ;
 955 }
 956
 957 /****************************************************************************/
 958
 959 rf24_crclength_e RF24::getCRCLength(void)
 960 {
 961   rf24_crclength_e result = RF24_CRC_DISABLED;
 962   uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
 963
 964   if ( config & _BV(EN_CRC ) )
 965   {
 966     if ( config & _BV(CRCO) )
 967       result = RF24_CRC_16;
 968     else
 969       result = RF24_CRC_8;
 970   }
 971
 972   return result;
 973 }
 974
 975 /****************************************************************************/
 976
 977 void RF24::disableCRC( void )
 978 {
 979   uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
 980   write_register( CONFIG, disable ) ;
 981 }
 982
 983 /****************************************************************************/
 984 void RF24::setRetries(uint8_t delay, uint8_t count)
 985 {
 986  write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
 987 }
 988
 989 // vim:ai:cin:sts=2 sw=2 ft=cpp
 990