RF24.cpp

   1 /*
   2  Copyright (C) 2011 James Coliz, Jr. <maniacbug@ymail.com>
   3
   4  This program is free software; you can redistribute it and/or
   5  modify it under the terms of the GNU General Public License
   6  version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #if ARDUINO < 100
  10 #include <WProgram.h>
  11 #else
  12 #include <Arduino.h>
  13 #endif
  14
  15 #include <SPI.h>
  16 #include "nRF24L01.h"
  17 #include "RF24.h"
  18
  19 #undef SERIAL_DEBUG
  20 #ifdef SERIAL_DEBUG
  21 #define IF_SERIAL_DEBUG(x) ({x;})
  22 #else
  23 #define IF_SERIAL_DEBUG(x)
  24 #endif
  25
  26 // Avoid spurious warnings
  27 #ifndef NATIVE
  28 #undef PROGMEM
  29 #define PROGMEM __attribute__(( section(".progmem.data") ))
  30 #undef PSTR
  31 #define PSTR(s) (__extension__({static prog_char __c[] PROGMEM = (s); &__c[0];}))
  32 #endif
  33
  34 /****************************************************************************/
  35
  36 void RF24::csn(int mode)
  37 {
  38   // Minimum ideal SPI bus speed is 2x data rate
  39   // If we assume 2Mbs data rate and 16Mhz clock, a
  40   // divider of 4 is the minimum we want.
  41   // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
  42   SPI.setBitOrder(MSBFIRST);
  43   SPI.setDataMode(SPI_MODE0);
  44   SPI.setClockDivider(SPI_CLOCK_DIV4);
  45   digitalWrite(csn_pin,mode);
  46 }
  47
  48 /****************************************************************************/
  49
  50 void RF24::ce(int level)
  51 {
  52   digitalWrite(ce_pin,level);
  53 }
  54
  55 /****************************************************************************/
  56
  57 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
  58 {
  59   uint8_t status;
  60
  61   csn(LOW);
  62   status = SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
  63   while ( len-- )
  64     *buf++ = SPI.transfer(0xff);
  65
  66   csn(HIGH);
  67
  68   return status;
  69 }
  70
  71 /****************************************************************************/
  72
  73 uint8_t RF24::read_register(uint8_t reg)
  74 {
  75   csn(LOW);
  76   SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
  77   uint8_t result = SPI.transfer(0xff);
  78
  79   csn(HIGH);
  80   return result;
  81 }
  82
  83 /****************************************************************************/
  84
  85 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
  86 {
  87   uint8_t status;
  88
  89   csn(LOW);
  90   status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
  91   while ( len-- )
  92     SPI.transfer(*buf++);
  93
  94   csn(HIGH);
  95
  96   return status;
  97 }
  98
  99 /****************************************************************************/
 100
 101 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
 102 {
 103   uint8_t status;
 104
 105   IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\n\r"),reg,value));
 106
 107   csn(LOW);
 108   status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
 109   SPI.transfer(value);
 110   csn(HIGH);
 111
 112   return status;
 113 }
 114
 115 /****************************************************************************/
 116
 117 uint8_t RF24::write_payload(const void* buf, uint8_t len)
 118 {
 119   uint8_t status;
 120
 121   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
 122
 123   uint8_t data_len = min(len,payload_size);
 124   uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
 125
 126   //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
 127
 128   csn(LOW);
 129   status = SPI.transfer( W_TX_PAYLOAD );
 130   while ( data_len-- )
 131     SPI.transfer(*current++);
 132   while ( blank_len-- )
 133     SPI.transfer(0);
 134   csn(HIGH);
 135
 136   return status;
 137 }
 138
 139 /****************************************************************************/
 140
 141 uint8_t RF24::read_payload(void* buf, uint8_t len)
 142 {
 143   uint8_t status;
 144   uint8_t* current = reinterpret_cast<uint8_t*>(buf);
 145
 146   uint8_t data_len = min(len,payload_size);
 147   uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
 148
 149   //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
 150
 151   csn(LOW);
 152   status = SPI.transfer( R_RX_PAYLOAD );
 153   while ( data_len-- )
 154     *current++ = SPI.transfer(0xff);
 155   while ( blank_len-- )
 156     SPI.transfer(0xff);
 157   csn(HIGH);
 158
 159   return status;
 160 }
 161
 162 /****************************************************************************/
 163
 164 uint8_t RF24::flush_rx(void)
 165 {
 166   uint8_t status;
 167
 168   csn(LOW);
 169   status = SPI.transfer( FLUSH_RX );
 170   csn(HIGH);
 171
 172   return status;
 173 }
 174
 175 /****************************************************************************/
 176
 177 uint8_t RF24::flush_tx(void)
 178 {
 179   uint8_t status;
 180
 181   csn(LOW);
 182   status = SPI.transfer( FLUSH_TX );
 183   csn(HIGH);
 184
 185   return status;
 186 }
 187
 188 /****************************************************************************/
 189
 190 uint8_t RF24::get_status(void)
 191 {
 192   uint8_t status;
 193
 194   csn(LOW);
 195   status = SPI.transfer( NOP );
 196   csn(HIGH);
 197
 198   return status;
 199 }
 200
 201 /****************************************************************************/
 202
 203 void RF24::print_status(uint8_t status)
 204 {
 205   printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\n\r"),
 206            status,
 207            (status & _BV(RX_DR))?1:0,
 208            (status & _BV(TX_DS))?1:0,
 209            (status & _BV(MAX_RT))?1:0,
 210            ((status >> RX_P_NO) & B111),
 211            (status & _BV(TX_FULL))?1:0
 212           );
 213 }
 214
 215 /****************************************************************************/
 216
 217 void RF24::print_observe_tx(uint8_t value)
 218 {
 219   printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\n\r"),
 220            value,
 221            (value >> PLOS_CNT) & B1111,
 222            (value >> ARC_CNT) & B1111
 223           );
 224 }
 225
 226 /****************************************************************************/
 227
 228 void RF24::print_byte_register(prog_char* name, uint8_t reg, uint8_t qty)
 229 {
 230   char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
 231   printf_P(PSTR("%S\t%c ="),name,extra_tab);
 232   while (qty--)
 233     printf_P(PSTR(" 0x%02x"),read_register(reg++));
 234   printf_P(PSTR("\n\r"));
 235 }
 236
 237 /****************************************************************************/
 238
 239 void RF24::print_address_register(prog_char* name, uint8_t reg, uint8_t qty)
 240 {
 241   char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
 242   printf_P(PSTR("%S\t%c ="),name,extra_tab);
 243
 244   while (qty--)
 245   {
 246     uint8_t buffer[5];
 247     read_register(reg++,buffer,sizeof buffer);
 248
 249     printf_P(PSTR(" 0x"));
 250     uint8_t* bufptr = buffer + sizeof buffer;
 251     while( --bufptr >= buffer )
 252       printf_P(PSTR("%02x"),*bufptr);
 253   }
 254
 255   printf_P(PSTR("\n\r"));
 256 }
 257
 258 /****************************************************************************/
 259
 260 RF24::RF24(uint8_t _cepin, uint8_t _cspin):
 261   ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false),
 262   payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
 263   pipe0_reading_address(0)
 264 {
 265 }
 266
 267 /****************************************************************************/
 268
 269 void RF24::setChannel(uint8_t channel)
 270 {
 271   // TODO: This method could take advantage of the 'wide_band' calculation
 272   // done in setChannel() to require certain channel spacing.
 273
 274   const uint8_t max_channel = 127;
 275   write_register(RF_CH,min(channel,max_channel));
 276 }
 277
 278 /****************************************************************************/
 279
 280 void RF24::setPayloadSize(uint8_t size)
 281 {
 282   const uint8_t max_payload_size = 32;
 283   payload_size = min(size,max_payload_size);
 284 }
 285
 286 /****************************************************************************/
 287
 288 uint8_t RF24::getPayloadSize(void)
 289 {
 290   return payload_size;
 291 }
 292
 293 /****************************************************************************/
 294
 295 void RF24::printDetails(void)
 296 {
 297   print_status(get_status());
 298
 299   print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
 300   print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
 301   print_address_register(PSTR("TX_ADDR"),TX_ADDR);
 302
 303   print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
 304   print_byte_register(PSTR("EN_AA"),EN_AA);
 305   print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
 306   print_byte_register(PSTR("RF_CH"),RF_CH);
 307   print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
 308   print_byte_register(PSTR("CONFIG"),CONFIG);
 309   print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
 310
 311   const char * rf24_datarate_e_str[] = { "1MBPS", "2MBPS", "250KBPS" };
 312   const char * rf24_model_e_str[] = { "nRF24L01", "nRF24L01+" } ;
 313   const char * rf24_crclength_e_str[] = { "Disabled", "8 bits", "16 bits" } ;
 314   const char * rf24_pa_dbm_e_str[] = { "PA_MIN", "PA_LOW", "LA_MED", "PA_HIGH"} ;
 315
 316   printf_P(PSTR("Data Rate\t = %s\n\r"),rf24_datarate_e_str[getDataRate()]);
 317   printf_P(PSTR("Model\t\t = %s\n\r"),rf24_model_e_str[isPVariant()]);
 318   printf_P(PSTR("CRC Length\t = %s\n\r"),rf24_crclength_e_str[getCRCLength()]);
 319   printf_P(PSTR("PA Power\t = %s\n\r"),rf24_pa_dbm_e_str[getPALevel()]);
 320 }
 321
 322 /****************************************************************************/
 323
 324 void RF24::begin(void)
 325 {
 326   // Initialize pins
 327   pinMode(ce_pin,OUTPUT);
 328   pinMode(csn_pin,OUTPUT);
 329
 330   // Initialize SPI bus
 331   SPI.begin();
 332
 333   ce(LOW);
 334   csn(HIGH);
 335
 336   // Must allow the radio time to settle else configuration bits will not necessarily stick.
 337   // This is actually only required following power up but some settling time also appears to
 338   // be required after resets too. For full coverage, we'll always assume the worst.
 339   // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
 340   // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
 341   // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
 342   delay( 5 ) ;
 343
 344   // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
 345   // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
 346   // sizes must never be used. See documentation for a more complete explanation.
 347   write_register(SETUP_RETR,(B0100 << ARD) | (B1111 << ARC));
 348
 349   // Restore our default PA level
 350   setPALevel( RF24_PA_MAX ) ;
 351
 352   // Determine if this is a p or non-p RF24 module and then
 353   // reset our data rate back to default value. This works
 354   // because a non-P variant won't allow the data rate to
 355   // be set to 250Kbps.
 356   if( setDataRate( RF24_250KBPS ) )
 357   {
 358     p_variant = true ;
 359   }
 360
 361   // Then set the data rate to the slowest (and most reliable) speed supported by all
 362   // hardware.
 363   setDataRate( RF24_1MBPS ) ;
 364
 365   // Initialize CRC and request 2-byte (16bit) CRC
 366   setCRCLength( RF24_CRC_16 ) ;
 367
 368   // Disable dynamic payloads, to match dynamic_payloads_enabled setting
 369   write_register(DYNPD,0);
 370
 371   // Reset current status
 372   // Notice reset and flush is the last thing we do
 373   write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 374
 375   // Set up default configuration.  Callers can always change it later.
 376   // This channel should be universally safe and not bleed over into adjacent
 377   // spectrum.
 378   setChannel(76);
 379
 380   // Flush buffers
 381   flush_rx();
 382   flush_tx();
 383 }
 384
 385 /****************************************************************************/
 386
 387 void RF24::startListening(void)
 388 {
 389   write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
 390   write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 391
 392   // Restore the pipe0 adddress, if exists
 393   if (pipe0_reading_address)
 394     write_register(RX_ADDR_P0, reinterpret_cast<const uint8_t*>(&pipe0_reading_address), 5);
 395
 396   // Flush buffers
 397   flush_rx();
 398   flush_tx();
 399
 400   // Go!
 401   ce(HIGH);
 402
 403   // wait for the radio to come up (130us actually only needed)
 404   delayMicroseconds(130);
 405 }
 406
 407 /****************************************************************************/
 408
 409 void RF24::stopListening(void)
 410 {
 411   ce(LOW);
 412   flush_tx();
 413   flush_rx();
 414 }
 415
 416 /****************************************************************************/
 417
 418 void RF24::powerDown(void)
 419 {
 420   write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
 421 }
 422
 423 /****************************************************************************/
 424
 425 void RF24::powerUp(void)
 426 {
 427   write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
 428 }
 429
 430 /******************************************************************/
 431
 432 bool RF24::write( const void* buf, uint8_t len )
 433 {
 434   bool result = false;
 435
 436   // Begin the write
 437   startWrite(buf,len);
 438
 439   // ------------
 440   // At this point we could return from a non-blocking write, and then call
 441   // the rest after an interrupt
 442
 443   // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
 444   // or MAX_RT (maximum retries, transmission failed).  Also, we'll timeout in case the radio
 445   // is flaky and we get neither.
 446
 447   // IN the end, the send should be blocking.  It comes back in 60ms worst case, or much faster
 448   // if I tighted up the retry logic.  (Default settings will be 1500us.
 449   // Monitor the send
 450   uint8_t observe_tx;
 451   uint8_t status;
 452   uint32_t sent_at = millis();
 453   const uint32_t timeout = 500; //ms to wait for timeout
 454   do
 455   {
 456     status = read_register(OBSERVE_TX,&observe_tx,1);
 457     IF_SERIAL_DEBUG(Serial.print(observe_tx,HEX));
 458   }
 459   while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) );
 460
 461   // The part above is what you could recreate with your own interrupt handler,
 462   // and then call this when you got an interrupt
 463   // ------------
 464
 465   // Call this when you get an interrupt
 466   // The status tells us three things
 467   // * The send was successful (TX_DS)
 468   // * The send failed, too many retries (MAX_RT)
 469   // * There is an ack packet waiting (RX_DR)
 470   bool tx_ok, tx_fail;
 471   whatHappened(tx_ok,tx_fail,ack_payload_available);
 472
 473   //printf("%u%u%u\n\r",tx_ok,tx_fail,ack_payload_available);
 474
 475   result = tx_ok;
 476   IF_SERIAL_DEBUG(Serial.print(result?"...OK.":"...Failed"));
 477
 478   // Handle the ack packet
 479   if ( ack_payload_available )
 480   {
 481     ack_payload_length = getDynamicPayloadSize();
 482     IF_SERIAL_DEBUG(Serial.print("[AckPacket]/"));
 483     IF_SERIAL_DEBUG(Serial.println(ack_payload_length,DEC));
 484   }
 485
 486   // Yay, we are done.
 487
 488   // Power down
 489   powerDown();
 490
 491   // Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
 492   flush_tx();
 493
 494   return result;
 495 }
 496 /****************************************************************************/
 497
 498 void RF24::startWrite( const void* buf, uint8_t len )
 499 {
 500   // Transmitter power-up
 501   write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
 502   delay(2);
 503
 504   // Send the payload
 505   write_payload( buf, len );
 506
 507   // Allons!
 508   ce(HIGH);
 509   delayMicroseconds(15);
 510   delay(2);
 511   ce(LOW);
 512 }
 513
 514 /****************************************************************************/
 515
 516 uint8_t RF24::getDynamicPayloadSize(void)
 517 {
 518   uint8_t result = 0;
 519
 520   csn(LOW);
 521   SPI.transfer( R_RX_PL_WID );
 522   result = SPI.transfer(0xff);
 523   csn(HIGH);
 524
 525   return result;
 526 }
 527
 528 /****************************************************************************/
 529
 530 bool RF24::available(void)
 531 {
 532   return available(NULL);
 533 }
 534
 535 /****************************************************************************/
 536
 537 bool RF24::available(uint8_t* pipe_num)
 538 {
 539   uint8_t status = get_status();
 540
 541   // Too noisy, enable if you really want lots o data!!
 542   //IF_SERIAL_DEBUG(print_status(status));
 543
 544   bool result = ( status & _BV(RX_DR) );
 545
 546   if (result)
 547   {
 548     // If the caller wants the pipe number, include that
 549     if ( pipe_num )
 550       *pipe_num = ( status >> RX_P_NO ) & B111;
 551
 552     // Clear the status bit
 553
 554     // ??? Should this REALLY be cleared now?  Or wait until we
 555     // actually READ the payload?
 556
 557     write_register(STATUS,_BV(RX_DR) );
 558
 559     // Handle ack payload receipt
 560     if ( status & _BV(TX_DS) )
 561     {
 562       write_register(STATUS,_BV(TX_DS));
 563     }
 564   }
 565
 566   return result;
 567 }
 568
 569 /****************************************************************************/
 570
 571 bool RF24::read( void* buf, uint8_t len )
 572 {
 573   // Fetch the payload
 574   read_payload( buf, len );
 575
 576   // was this the last of the data available?
 577   return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
 578 }
 579
 580 /****************************************************************************/
 581
 582 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
 583 {
 584   // Read the status & reset the status in one easy call
 585   // Or is that such a good idea?
 586   uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 587
 588   // Report to the user what happened
 589   tx_ok = status & _BV(TX_DS);
 590   tx_fail = status & _BV(MAX_RT);
 591   rx_ready = status & _BV(RX_DR);
 592 }
 593
 594 /****************************************************************************/
 595
 596 void RF24::openWritingPipe(uint64_t value)
 597 {
 598   // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
 599   // expects it LSB first too, so we're good.
 600
 601   write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), 5);
 602   write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), 5);
 603
 604   const uint8_t max_payload_size = 32;
 605   write_register(RX_PW_P0,min(payload_size,max_payload_size));
 606 }
 607
 608 /****************************************************************************/
 609
 610 void RF24::openReadingPipe(uint8_t child, uint64_t address)
 611 {
 612   const uint8_t child_pipe[] =
 613   {
 614     RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
 615   };
 616   const uint8_t child_payload_size[] =
 617   {
 618     RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
 619   };
 620   const uint8_t child_pipe_enable[] =
 621   {
 622     ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
 623   };
 624
 625   // If this is pipe 0, cache the address.  This is needed because
 626   // openWritingPipe() will overwrite the pipe 0 address, so
 627   // startListening() will have to restore it.
 628   if (child == 0)
 629     pipe0_reading_address = address;
 630
 631   if (child <= 6)
 632   {
 633     // For pipes 2-5, only write the LSB
 634     if ( child < 2 )
 635       write_register(child_pipe[child], reinterpret_cast<const uint8_t*>(&address), 5);
 636     else
 637       write_register(child_pipe[child], reinterpret_cast<const uint8_t*>(&address), 1);
 638
 639     write_register(child_payload_size[child],payload_size);
 640
 641     // Note it would be more efficient to set all of the bits for all open
 642     // pipes at once.  However, I thought it would make the calling code
 643     // more simple to do it this way.
 644     write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(child_pipe_enable[child]));
 645   }
 646 }
 647
 648 /****************************************************************************/
 649
 650 void RF24::toggle_features(void)
 651 {
 652   csn(LOW);
 653   SPI.transfer( ACTIVATE );
 654   SPI.transfer( 0x73 );
 655   csn(HIGH);
 656 }
 657
 658 /****************************************************************************/
 659
 660 void RF24::enableDynamicPayloads(void)
 661 {
 662   // Enable dynamic payload throughout the system
 663   write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
 664
 665   // If it didn't work, the features are not enabled
 666   if ( ! read_register(FEATURE) )
 667   {
 668     // So enable them and try again
 669     toggle_features();
 670     write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
 671   }
 672
 673   IF_SERIAL_DEBUG(printf("FEATURE=%i\n\r",read_register(FEATURE)));
 674
 675   // Enable dynamic payload on all pipes
 676   //
 677   // Not sure the use case of only having dynamic payload on certain
 678   // pipes, so the library does not support it.
 679   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
 680
 681   dynamic_payloads_enabled = true;
 682 }
 683
 684 /****************************************************************************/
 685
 686 void RF24::enableAckPayload(void)
 687 {
 688   //
 689   // enable ack payload and dynamic payload features
 690   //
 691
 692   write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
 693
 694   // If it didn't work, the features are not enabled
 695   if ( ! read_register(FEATURE) )
 696   {
 697     // So enable them and try again
 698     toggle_features();
 699     write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
 700   }
 701
 702   IF_SERIAL_DEBUG(printf("FEATURE=%i\n\r",read_register(FEATURE)));
 703
 704   //
 705   // Enable dynamic payload on pipes 0 & 1
 706   //
 707
 708   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
 709 }
 710
 711 /****************************************************************************/
 712
 713 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
 714 {
 715   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
 716
 717   csn(LOW);
 718   SPI.transfer( W_ACK_PAYLOAD | ( pipe & B111 ) );
 719   const uint8_t max_payload_size = 32;
 720   uint8_t data_len = min(len,max_payload_size);
 721   while ( data_len-- )
 722     SPI.transfer(*current++);
 723
 724   csn(HIGH);
 725 }
 726
 727 /****************************************************************************/
 728
 729 bool RF24::isAckPayloadAvailable(void)
 730 {
 731   bool result = ack_payload_available;
 732   ack_payload_available = false;
 733   return result;
 734 }
 735
 736 /****************************************************************************/
 737
 738 bool RF24::isPVariant(void)
 739 {
 740   return p_variant ;
 741 }
 742
 743 /****************************************************************************/
 744
 745 void RF24::setAutoAck(bool enable)
 746 {
 747   if ( enable )
 748     write_register(EN_AA, B111111);
 749   else
 750     write_register(EN_AA, 0);
 751 }
 752
 753 /****************************************************************************/
 754
 755 void RF24::setAutoAck( uint8_t pipe, bool enable )
 756 {
 757   if ( pipe <= 6 )
 758   {
 759     uint8_t en_aa = read_register( EN_AA ) ;
 760     if( enable )
 761     {
 762       en_aa |= _BV(pipe) ;
 763     }
 764     else
 765     {
 766       en_aa &= ~_BV(pipe) ;
 767     }
 768     write_register( EN_AA, en_aa ) ;
 769   }
 770 }
 771
 772 /****************************************************************************/
 773
 774 bool RF24::testCarrier(void)
 775 {
 776   return ( read_register(CD) & 1 );
 777 }
 778
 779 /****************************************************************************/
 780
 781 bool RF24::testRPD(void)
 782 {
 783   return ( read_register(RPD) & 1 ) ;
 784 }
 785
 786 /****************************************************************************/
 787
 788 void RF24::setPALevel(rf24_pa_dbm_e level)
 789 {
 790   uint8_t setup = read_register(RF_SETUP) ;
 791   setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 792
 793   switch( level )
 794   {
 795   case RF24_PA_MAX:
 796     setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 797     break ;
 798
 799   case RF24_PA_HIGH:
 800     setup |= _BV(RF_PWR_HIGH) ;
 801     break ;
 802
 803   case RF24_PA_LOW:
 804     setup |= _BV(RF_PWR_LOW) ;
 805     break ;
 806
 807   case RF24_PA_MIN:
 808     break ;
 809
 810   case RF24_PA_ERROR:
 811     // On error, go to maximum PA
 812     setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 813     break ;
 814   }
 815
 816   write_register( RF_SETUP, setup ) ;
 817 }
 818
 819 /****************************************************************************/
 820
 821 rf24_pa_dbm_e RF24::getPALevel(void)
 822 {
 823   rf24_pa_dbm_e result = RF24_PA_ERROR ;
 824   uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
 825
 826   switch( power )
 827   {
 828   case (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)):
 829     result = RF24_PA_MAX ;
 830     break ;
 831
 832   case _BV(RF_PWR_HIGH):
 833     result = RF24_PA_HIGH ;
 834     break ;
 835
 836   case _BV(RF_PWR_LOW):
 837     result = RF24_PA_LOW ;
 838     break ;
 839
 840   default:
 841     result = RF24_PA_MIN ;
 842     break ;
 843   }
 844
 845   return result ;
 846 }
 847
 848 /****************************************************************************/
 849
 850 bool RF24::setDataRate(rf24_datarate_e speed)
 851 {
 852   bool result = false;
 853   uint8_t setup = read_register(RF_SETUP) ;
 854
 855   // HIGH and LOW '00' is 1Mbs - our default
 856   wide_band = false ;
 857   setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
 858   if( speed == RF24_250KBPS )
 859   {
 860     // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
 861     // Making it '10'.
 862     wide_band = false ;
 863     setup |= _BV( RF_DR_LOW ) ;
 864   }
 865   else
 866   {
 867     // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
 868     // Making it '01'
 869     if ( speed == RF24_2MBPS )
 870     {
 871       wide_band = true ;
 872       setup |= _BV(RF_DR_HIGH);
 873     }
 874     else
 875     {
 876       // 1Mbs
 877       wide_band = false ;
 878     }
 879   }
 880   write_register(RF_SETUP,setup);
 881
 882   // Verify our result
 883   if ( read_register(RF_SETUP) == setup )
 884   {
 885     result = true;
 886   }
 887   else
 888   {
 889     wide_band = false;
 890   }
 891
 892   return result;
 893 }
 894
 895 /****************************************************************************/
 896
 897 rf24_datarate_e RF24::getDataRate( void )
 898 {
 899   rf24_datarate_e result ;
 900   uint8_t setup = read_register(RF_SETUP) ;
 901
 902   // Order matters in our case below
 903   switch( setup & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) )
 904   {
 905   case _BV(RF_DR_LOW):
 906     // '10' = 250KBPS
 907     result = RF24_250KBPS ;
 908     break ;
 909
 910   case _BV(RF_DR_HIGH):
 911     // '01' = 2MBPS
 912     result = RF24_2MBPS ;
 913     break ;
 914
 915   default:
 916     // '00' = 1MBPS
 917     result = RF24_1MBPS ;
 918     break ;
 919   }
 920
 921   return result ;
 922 }
 923
 924 /****************************************************************************/
 925
 926 void RF24::setCRCLength(rf24_crclength_e length)
 927 {
 928   uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
 929
 930   switch (length)
 931   {
 932     case RF24_CRC_DISABLED:
 933       break;
 934
 935     case RF24_CRC_8:
 936       config |= _BV(EN_CRC);
 937       break;
 938
 939     case RF24_CRC_16:
 940     default:
 941       config |= _BV(EN_CRC);
 942       config |= _BV( CRCO );
 943       break;
 944   }
 945
 946   write_register( CONFIG, config ) ;
 947 }
 948
 949 /****************************************************************************/
 950
 951 rf24_crclength_e RF24::getCRCLength(void)
 952 {
 953   rf24_crclength_e result = RF24_CRC_DISABLED;
 954   uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
 955
 956   if ( config & _BV(EN_CRC ) )
 957   {
 958     if ( config & _BV(CRCO) )
 959       result = RF24_CRC_16;
 960     else
 961       result = RF24_CRC_8;
 962   }
 963
 964   return result;
 965 }
 966
 967 /****************************************************************************/
 968
 969 void RF24::disableCRC( void )
 970 {
 971   uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
 972   write_register( CONFIG, disable ) ;
 973 }
 974
 975 /****************************************************************************/
 976 void RF24::setRetries(uint8_t delay, uint8_t count)
 977 {
 978  write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
 979 }
 980
 981 // vim:ai:cin:sts=2 sw=2 ft=cpp
 982