1 # MUSB Verilog HDL design files
3 Verilog HDL design files for the MUSB project: MIPS32-compliant processor, I/O peripherals and SoC (MUSoC).
9 ├── arbiter/ : N-Masters, 1-Slave arbiter.
10 ├── clk_generator/ : Clock generation.
11 ├── fifo/ : FIFO module.
12 ├── gpio/ : General Purpose Input Output, 4 x 8-bits module, with edge detection (interrupt).
13 ├── include/ : Opcodes and processor configuration.
14 ├── mem/ : Internal memory for synthesis.
15 ├── musb/ : The RTL files for the processor.
16 ├── musoc/ : SoC implementation (top file).
17 ├── mux_switch/ : 1-Master, N-Slaves bus multiplexer.
19 ├── rst_generator/ : Reset generator.
20 ├── uart/ : 115200 baud, 8-N-1. Includes a hardware bootloader.