Restructure the code
[AROS.git] / rom / usb / pciusbhc / xhci / pcixhci_intern.h
blobe6257ba648747240cb2fc36df1ae92135a443e1e
1 /*
2 Copyright © 2014, The AROS Development Team. All rights reserved.
3 $Id$
5 Desc:
6 Lang: English
7 */
8 #ifndef PCIXHCI_INTERN_H
9 #define PCIXHCI_INTERN_H
11 #include <aros/debug.h>
12 #include <aros/macros.h>
13 #include <aros/asmcall.h>
14 #include <aros/symbolsets.h>
16 #include <proto/oop.h>
17 #include <proto/exec.h>
18 #include <proto/stdc.h>
19 #include <proto/arossupport.h>
21 #include <devices/usb.h>
22 #include <devices/usb_hub.h>
23 #include <devices/newstyle.h>
24 #include <devices/usbhardware.h>
26 #include <asm/io.h>
27 #include <inttypes.h>
29 #include <hidd/pci.h>
30 #include <hidd/hidd.h>
32 #include LC_LIBDEFS_FILE
34 /* Number of host controllers */
35 #define PCIXHCI_NUMCONTROLLERS 1
37 /* Number of ports per host controller (USB2.0/USB3.0) */
38 //#define PCIXHCI_NUMPORTS20 2
39 #define PCIXHCI_NUMPORTS30 4
41 #define RC_OK 0
42 #define RC_DONTREPLY -1
44 #define MYBUG_LEVEL 0
45 #define mybug(l, x) D(if ((l>=MYBUG_LEVEL)||(l==-1)) { do { { bug x; } } while (0); } )
46 #define mybug_unit(l, x) D(if ((l>=MYBUG_LEVEL)||(l==-1)) { do { { bug("%s %s: ", unit->name, __FUNCTION__); bug x; } } while (0); } )
48 #define PCI_BASE_CLASS_SERIAL 0x0c
49 #define PCI_SUB_CLASS_USB 0x03
50 #define PCI_INTERFACE_XHCI 0x30
52 struct PCIXHCIPort {
53 struct Node node;
54 char name[256];
55 ULONG number;
56 ULONG state;
59 struct PCIXHCIUnit {
60 struct Node node;
61 char name[256];
62 ULONG number;
63 ULONG state;
65 struct PCIXHCIRootHub {
66 struct List port_list;
67 ULONG port_count;
69 UWORD addr;
71 struct UsbStdDevDesc devdesc;
73 struct RHConfig {
74 struct UsbStdCfgDesc cfgdesc;
75 struct UsbStdIfDesc ifdesc;
76 struct UsbStdEPDesc epdesc;
77 } config;
79 union {
80 struct UsbHubDesc usb20;
81 struct UsbSSHubDesc usb30;
82 } hubdesc;
84 } roothub;
86 struct PCIXHCIHostController {
87 OOP_Object *pcidevice;
88 OOP_Object *pcidriver;
90 IPTR bus;
91 IPTR dev;
92 IPTR sub;
93 IPTR intline;
95 } hc;
99 struct PCIXHCIBase {
101 struct Library library;
102 struct List unit_list;
104 OOP_Object *pci;
105 OOP_AttrBase HiddAB;
106 OOP_AttrBase HiddPCIDeviceAB;
110 #undef HiddAttrBase
111 #undef HiddPCIDeviceAttrBase
112 #define HiddAttrBase (LIBBASE->HiddAB)
113 #define HiddPCIDeviceAttrBase (LIBBASE->HiddPCIDeviceAB)
115 BOOL PCIXHCI_Discover(struct PCIXHCIBase *PCIXHCIBase);
116 struct PCIXHCIUnit *PCIXHCI_AddNewUnit(ULONG unitnum, UWORD bcdusb);
117 struct PCIXHCIPort *PCIXHCI_AddNewPort(struct PCIXHCIUnit *unit, ULONG portnum);
119 BOOL cmdAbortIO(struct IOUsbHWReq *ioreq);
120 WORD cmdUsbReset(struct IOUsbHWReq *ioreq);
121 WORD cmdNSDeviceQuery(struct IOStdReq *ioreq);
122 WORD cmdQueryDevice(struct IOUsbHWReq *ioreq);
123 WORD cmdControlXFer(struct IOUsbHWReq *ioreq);
124 WORD cmdControlXFerRootHub(struct IOUsbHWReq *ioreq);
125 WORD cmdIntXFer(struct IOUsbHWReq *ioreq);
126 WORD cmdIntXFerRootHub(struct IOUsbHWReq *ioreq);
127 WORD cmdGetString(struct IOUsbHWReq *ioreq, char *cstring);
129 #endif /* PCIXHCI_INTERN_H */