test/getcpuinfo.c

   1 #include <proto/exec.h>
   2 #include <resources/processor.h>
   3 #include <stdio.h>
   4 #if !defined(STATICBUILD)
   5 #include <proto/processor.h>
   6
   7 APTR ProcessorBase = NULL;
   8 #else
   9 #include "processor_intern.h"
  10 struct ProcessorBase ProcBase;
  11 void Processor_GetCPUInfo(struct TagItem * tagList, struct ProcessorBase * ProcessorBase);
  12 LONG Processor_Init(struct ProcessorBase * ProcessorBase);
  13 #define GetCPUInfo(x) Processor_GetCPUInfo(x, &ProcBase)
  14 #endif
  15
  16 static ULONG getcpucount()
  17 {
  18     ULONG cpucount = 0;
  19     struct TagItem tags [] =
  20     {
  21         {GCIT_NumberOfProcessors, (IPTR)&cpucount},
  22         {TAG_DONE, TAG_DONE}
  23     };
  24
  25     GetCPUInfo(tags);
  26
  27     printf("CPU Count: %d\n", cpucount);
  28
  29     return cpucount;
  30 }
  31
  32 struct TagDescription
  33 {
  34     ULONG Value;
  35     CONST_STRPTR Description;
  36 };
  37
  38 struct TagDescription VectorUnit [] =
  39 {
  40     { VECTORTYPE_NONE, "None"},
  41     { VECTORTYPE_ALTIVEC, "AltiVec"},
  42     { VECTORTYPE_VMX, "VMX"},
  43     { VECTORTYPE_MMX, "MMX"},
  44     { VECTORTYPE_SSE, "SSE"},
  45     { VECTORTYPE_SSE2, "SSE2"},
  46     { VECTORTYPE_SSE3, "SSE3"},
  47     { VECTORTYPE_SSSE3, "SSSE3"},
  48     { VECTORTYPE_SSE41, "SSE41"},
  49     { VECTORTYPE_SSE42, "SSE42"},
  50     { VECTORTYPE_MMXEXT, "MMX Ext"},
  51     { VECTORTYPE_3DNOW, "3DNow"},
  52     { VECTORTYPE_3DNOWEXT, "3DNow Ext"},
  53     { VECTORTYPE_SSE4A, "SSE4A"},
  54     { 0, NULL }
  55 };
  56
  57 struct TagDescription ProcessorFamily [] =
  58 {
  59     { CPUFAMILY_UNKNOWN, "Unknown" },
  60     { CPUFAMILY_60X, "PowerPC 60X" },
  61     { CPUFAMILY_7X0, "PowerPC 7X0" },
  62     { CPUFAMILY_74XX, "PowerPC 74XX" },
  63     { CPUFAMILY_4XX, "PowerPC 4XX" },
  64     { CPUFAMILY_AMD_K5, "AMD K5" },
  65     { CPUFAMILY_AMD_K6, "AMD K6" },
  66     { CPUFAMILY_AMD_K7, "AMD K7" },
  67     { CPUFAMILY_AMD_K8, "AMD K8" },
  68     { CPUFAMILY_AMD_K9, "AMD K9" },
  69     { CPUFAMILY_AMD_K10, "AMD K10" },
  70     { CPUFAMILY_INTEL_486, "Intel 486" },
  71     { CPUFAMILY_INTEL_PENTIUM, "Intel Pentium" },
  72     { CPUFAMILY_INTEL_PENTIUM_PRO, "Intel Pentium Pro" },
  73     { CPUFAMILY_INTEL_PENTIUM4, "Intel Pentium 4"},
  74     { 0, NULL },
  75 };
  76
  77 struct TagDescription ProcessorArchitecture [] =
  78 {
  79     { PROCESSORARCH_UNKNOWN, "Unknown" },
  80     { PROCESSORARCH_M68K, "Motorola 68K" },
  81     { PROCESSORARCH_PPC, "PowerPC" },
  82     { PROCESSORARCH_X86, "X86" },
  83     { PROCESSORARCH_ARM, "ARM" },
  84     { 0, NULL }
  85 };
  86
  87 struct TagDescription CurrentEndianness [] =
  88 {
  89     { ENDIANNESS_UNKNOWN, "Unknown" },
  90     { ENDIANNESS_LE, "LE" },
  91     { ENDIANNESS_BE, "BE" },
  92     { 0, NULL}
  93 };
  94
  95 struct TagDescription ProcessorFeatures [] =
  96 {
  97     { GCIT_SupportsFPU, "FPU" },
  98     { GCIT_SupportsAltiVec, "AltiVec" },
  99     { GCIT_SupportsVMX, "VMX" },
 100     { GCIT_SupportsMMX, "MMX" },
 101     { GCIT_SupportsMMXEXT, "AMD MMX Entensions" },
 102     { GCIT_Supports3DNOW, "3DNow!" },
 103     { GCIT_Supports3DNOWEXT, "AMD 3DNow! Extensions" },
 104     { GCIT_SupportsSSE, "SSE" },
 105     { GCIT_SupportsSSE2, "SSE2" },
 106     { GCIT_SupportsSSE3, "SSE3" },
 107     { GCIT_SupportsSSSE3, "SSSE3" },
 108     { GCIT_SupportsSSE41, "SSE4.1" },
 109     { GCIT_SupportsSSE42, "SSE4.2" },
 110     { GCIT_SupportsSSE4A, "SSE4a" },
 111     { GCIT_SupportsVME, "Virtual Mode Extension" },
 112     { GCIT_SupportsPSE, "Page Size Extension" },
 113     { GCIT_SupportsPAE, "Physical Address Extension" },
 114     { GCIT_SupportsCX8, "CMPXCHG8 Instruction" },
 115     { GCIT_SupportsAPIC, "APIC" },
 116     { GCIT_SupportsCMOV, "Conditional Move Instruction" },
 117     { GCIT_SupportsPSE36, "36-bit Page Size Extension" },
 118     { GCIT_SupportsCLFSH, "CLFLUSH Instruction" },
 119     { GCIT_SupportsACPI, "ACPI" },
 120     { GCIT_SupportsFXSR, "FXSAVE and FXSTOR Instructions" },
 121     { GCIT_SupportsHTT, "Hyper-Threading Technology" },
 122     { GCIT_SupportsCX16, "CMPXCHG16B Instruction" },
 123     { GCIT_SupportsVirtualization, "Virtualization Technology" },
 124     { GCIT_SupportsNoExecutionBit, "No-Execution Page Bit" },
 125     { GCIT_Supports64BitMode, "64-bit Capable (x86-64)" },
 126     { GCIT_SupportsMSR, "MSR (Model Specific Registers)" },
 127     { 0, NULL }
 128 };
 129
 130 CONST_STRPTR GetDescription(struct TagDescription * table, ULONG value)
 131 {
 132     static CONST_STRPTR undefined = "Undefined";
 133
 134     LONG i = 0;
 135     while (table[i].Description != NULL)
 136     {
 137         if (table[i].Value == value)
 138             return table[i].Description;
 139         i++;
 140     }
 141
 142     return undefined;
 143 }
 144
 145 static void printcpuinformation(ULONG index)
 146 {
 147     CONST_STRPTR modelstring;
 148     ULONG family, vectorunit;
 149     ULONG i = 0;
 150     ULONG l1size, l1datasize, l1instrsize, l2size, l3size, cachelinesize;
 151     ULONG architecture, endianness;
 152     UQUAD currentspeed, fsbspeed;
 153
 154     struct TagItem tags [] =
 155     {
 156         {GCIT_SelectedProcessor, index},
 157         {GCIT_ModelString, (IPTR)&modelstring},
 158         {GCIT_Family, (IPTR)&family},
 159         {GCIT_VectorUnit, (IPTR)&vectorunit},
 160         {GCIT_L1CacheSize, (IPTR)&l1size},
 161         {GCIT_L1DataCacheSize, (IPTR)&l1datasize},
 162         {GCIT_L1InstructionCacheSize, (IPTR)&l1instrsize},
 163         {GCIT_L2CacheSize, (IPTR)&l2size},
 164         {GCIT_L3CacheSize, (IPTR)&l3size},
 165         {GCIT_CacheLineSize, (IPTR)&cachelinesize},
 166         {GCIT_Architecture, (IPTR)&architecture},
 167         {GCIT_Endianness, (IPTR)&endianness},
 168         {GCIT_ProcessorSpeed, (IPTR)&currentspeed},
 169         {GCIT_FrontsideSpeed, (IPTR)&fsbspeed},
 170         {TAG_DONE, TAG_DONE}
 171     };
 172
 173     GetCPUInfo(tags);
 174
 175     printf("CPU: %d\n", index);
 176     printf("Family: %d\n", family);
 177     printf("FamilyString: %s\n", GetDescription(ProcessorFamily, family));
 178     printf("ModelString: %s\n", modelstring);
 179     printf("Vector Unit: %s\n", GetDescription(VectorUnit, vectorunit));
 180     printf("Architecture: %s\n", GetDescription(ProcessorArchitecture, architecture));
 181     printf("Endianness: %s\n", GetDescription(CurrentEndianness, endianness));
 182
 183     printf("Current Speed: %u Mhz\n", (ULONG)(currentspeed / 1000000));
 184     printf("Frontside Bus Speed: %u Mhz\n", (ULONG)(fsbspeed / 1000000));
 185
 186     printf("L1CacheSize: %d kB\n", l1size);
 187     printf("L1DataCacheSize: %d kB\n", l1datasize);
 188     printf("L1InstructionCacheSize: %d kB\n", l1instrsize);
 189     printf("L2CacheSize: %d kB\n", l2size);
 190     printf("L3CacheSize: %d kB\n", l3size);
 191     printf("CacheLineSize: %d B\n", cachelinesize);
 192
 193     printf("Features:\n");
 194     i = 0;
 195     while(ProcessorFeatures[i].Description != NULL)
 196     {
 197         BOOL check = FALSE;
 198         struct TagItem ftags [] =
 199         {
 200             { GCIT_SelectedProcessor, index },
 201             { ProcessorFeatures[i].Value, (IPTR)&check },
 202             { TAG_DONE, TAG_DONE }
 203         };
 204
 205         GetCPUInfo(ftags);
 206
 207         if (check)
 208             printf("    [%s]\n", ProcessorFeatures[i].Description);
 209         i++;
 210     }
 211 }
 212
 213 int main(void)
 214 {
 215     ULONG cpus = 0;
 216     ULONG index = 0;
 217
 218 #if !defined(STATICBUILD)
 219     if ((ProcessorBase = OpenResource(PROCESSORNAME)) == NULL)
 220     {
 221         printf("Not able to open %s\n", PROCESSORNAME);
 222         return 1;
 223     }
 224 #else
 225     Processor_Init(&ProcBase);
 226 #endif
 227
 228     cpus = getcpucount();
 229
 230     for(index = 0; index < cpus; index++)
 231         printcpuinformation(index);
 232
 233     return 0;
 234 }