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[AROS.git] / rom / usb / pciusb / pciusb.h
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1 #ifndef PCIUSB_H
2 #define PCIUSB_H
4 /*
5 *----------------------------------------------------------------------------
6 * Includes for pciusb.device
7 *----------------------------------------------------------------------------
8 * By Chris Hodges <chrisly@platon42.de>
9 */
11 #include LC_LIBDEFS_FILE
13 #include <aros/libcall.h>
14 #include <aros/asmcall.h>
15 #include <aros/symbolsets.h>
17 #include <exec/types.h>
18 #include <exec/lists.h>
19 #include <exec/memory.h>
20 #include <exec/libraries.h>
21 #include <exec/interrupts.h>
22 #include <exec/semaphores.h>
23 #include <exec/execbase.h>
24 #include <exec/devices.h>
25 #include <exec/io.h>
26 #include <exec/ports.h>
27 #include <exec/errors.h>
28 #include <exec/resident.h>
29 #include <exec/initializers.h>
30 #include <dos/dos.h>
32 #include <devices/timer.h>
33 #include <utility/utility.h>
35 #include <devices/usbhardware.h>
36 #include <devices/newstyle.h>
38 #include <oop/oop.h>
40 #include "debug.h"
42 /* Reply the iorequest with success */
43 #define RC_OK 0
45 /* Magic cookie, don't set error fields & don't reply the ioreq */
46 #define RC_DONTREPLY -1
48 #define MAX_ROOT_PORTS 16
50 #define PCI_CLASS_SERIAL_USB 0x0c03
52 /* The unit node - private */
53 struct PCIUnit
55 struct Unit hu_Unit;
56 LONG hu_UnitNo;
58 struct PCIDevice *hu_Device; /* Uplink */
60 struct MsgPort *hu_MsgPort;
61 struct timerequest *hu_TimerReq; /* Timer I/O Request */
63 struct timerequest hu_LateIOReq; /* Timer I/O Request */
64 struct MsgPort hu_LateMsgPort;
66 struct timerequest hu_NakTimeoutReq;
67 struct MsgPort hu_NakTimeoutMsgPort;
68 struct Interrupt hu_NakTimeoutInt;
70 BOOL hu_UnitAllocated; /* Unit opened */
72 ULONG hu_DevID; /* Device ID (BusID+DevNo) */
73 struct List hu_Controllers; /* List of controllers */
74 UWORD hu_RootHub11Ports;
75 UWORD hu_RootHub20Ports;
76 UWORD hu_RootHubPorts;
77 UWORD hu_RootHubAddr; /* Root Hub Address */
78 UWORD hu_RootPortChanges; /* Merged root hub changes */
79 ULONG hu_FrameCounter; /* Common frame counter */
80 struct List hu_RHIOQueue; /* Root Hub Pending IO Requests */
82 struct PCIController *hu_PortMap11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 controller */
83 struct PCIController *hu_PortMap20[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 2.0 controller */
84 UBYTE hu_PortNum11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 companion controller port */
85 UBYTE hu_EhciOwned[MAX_ROOT_PORTS]; /* TRUE, if currently owned by EHCI */
86 UBYTE hu_ProductName[80]; /* for Query device */
87 struct PCIController *hu_DevControllers[128]; /* maps from Device address to controller */
88 struct IOUsbHWReq *hu_DevBusyReq[128*16*2]; /* pointer to io assigned to the Endpoint */
89 ULONG hu_NakTimeoutFrame[128*16*2]; /* Nak Timeout framenumber */
90 UBYTE hu_DevDataToggle[128*16*2]; /* Data toggle bit for endpoints */
93 #define HCITYPE_UHCI 0x00
94 #define HCITYPE_OHCI 0x10
95 #define HCITYPE_EHCI 0x20
97 struct PCIController
99 struct Node hc_Node;
100 struct PCIDevice *hc_Device; /* Uplink */
101 struct PCIUnit *hc_Unit; /* Uplink */
103 OOP_Object *hc_PCIDeviceObject;
104 OOP_Object *hc_PCIDriverObject;
105 ULONG hc_DevID;
106 UWORD hc_FunctionNum;
107 UWORD hc_HCIType;
108 UWORD hc_NumPorts;
109 UWORD hc_Flags; /* See below */
111 volatile APTR hc_RegBase;
113 APTR hc_PCIMem;
114 ULONG hc_PCIMemSize;
115 IPTR hc_PCIVirtualAdjust;
116 IPTR hc_PCIIntLine;
117 struct Interrupt hc_PCIIntHandler;
118 ULONG hc_PCIIntEnMask;
120 ULONG *hc_UhciFrameList;
121 struct UhciQH *hc_UhciQHPool;
122 struct UhciTD *hc_UhciTDPool;
124 struct UhciQH *hc_UhciCtrlQH;
125 struct UhciQH *hc_UhciBulkQH;
126 struct UhciQH *hc_UhciIntQH[9];
127 struct UhciTD *hc_UhciIsoTD;
128 struct UhciQH *hc_UhciTermQH;
130 ULONG hc_EhciUsbCmd;
131 ULONG *hc_EhciFrameList;
132 struct EhciQH *hc_EhciQHPool;
133 struct EhciTD *hc_EhciTDPool;
135 struct EhciQH *hc_EhciAsyncQH;
136 struct EhciQH *hc_EhciIntQH[11];
137 struct EhciQH *hc_EhciTermQH;
138 volatile BOOL hc_AsyncAdvanced;
139 struct EhciQH *hc_EhciAsyncFreeQH;
140 struct EhciTD *hc_ShortPktEndTD;
142 struct OhciED *hc_OhciCtrlHeadED;
143 struct OhciED *hc_OhciCtrlTailED;
144 struct OhciED *hc_OhciBulkHeadED;
145 struct OhciED *hc_OhciBulkTailED;
146 struct OhciED *hc_OhciIntED[5];
147 struct OhciED *hc_OhciTermED;
148 struct OhciTD *hc_OhciTermTD;
149 struct OhciHCCA *hc_OhciHCCA;
150 struct OhciED *hc_OhciEDPool;
151 struct OhciTD *hc_OhciTDPool;
152 struct OhciED *hc_OhciAsyncFreeED;
153 ULONG hc_OhciDoneQueue;
154 struct List hc_OhciRetireQueue;
156 ULONG hc_FrameCounter;
157 struct List hc_TDQueue;
158 struct List hc_AbortQueue;
159 struct List hc_PeriodicTDQueue;
160 struct List hc_CtrlXFerQueue;
161 struct List hc_IntXFerQueue;
162 struct List hc_IsoXFerQueue;
163 struct List hc_BulkXFerQueue;
165 struct Interrupt hc_CompleteInt;
166 struct Interrupt hc_ResetInt;
168 UBYTE hc_PortNum20[MAX_ROOT_PORTS]; /* Global Port number the local controller port corresponds with */
170 UWORD hc_PortChangeMap[MAX_ROOT_PORTS]; /* Port Change Map */
172 BOOL hc_complexrouting;
173 ULONG hc_portroute;
177 /* hc_Flags */
178 #define HCF_ALLOCATED 0x0001 /* PCI board allocated */
179 #define HCF_ONLINE 0x0002 /* Online */
180 #define HCF_STOP_BULK 0x0004 /* Bulk transfers stopped */
181 #define HCF_STOP_CTRL 0x0008 /* Control transfers stopped */
182 #define HCF_ABORT 0x0010 /* Aborted requests available */
184 /* The device node - private
186 struct PCIDevice
188 struct Library hd_Library; /* standard */
189 UWORD hd_Flags; /* various flags */
191 struct UtilityBase *hd_UtilityBase; /* for tags etc */
193 struct List hd_TempHCIList;
194 OOP_Object *hd_PCIHidd;
195 OOP_AttrBase hd_HiddAB;
196 OOP_AttrBase hd_HiddPCIDeviceAB;
197 OOP_MethodID hd_HiddPCIDeviceMB;
199 BOOL hd_ScanDone; /* PCI scan done? */
200 APTR hd_MemPool; /* Memory Pool */
202 struct List hd_Units; /* List of units */
205 /* hd_Flags */
206 #define HDF_FORCEPOWER 0x01
208 #endif /* PCIUSB_H */