compiler/include/hardware/ahci.h

   1 #ifndef AHCI_HBA_H
   2 #define AHCI_HBA_H
   3
   4 /*
   5     Copyright © 2010, The AROS Development Team. All rights reserved
   6     $Id$
   7 */
   8
   9 #include <exec/types.h>
  10 #include <inttypes.h>
  11
  12 #ifndef __packed
  13 #ifdef __GNUC__
  14 #define __packed __attribute__((__packed__))
  15 #else
  16 #define __packed
  17 #endif
  18 #endif
  19
  20 #define AHCI_VERSION_0_95   0x00000095
  21 #define AHCI_VERSION_1_00   0x00010000
  22 #define AHCI_VERSION_1_10   0x00010100
  23 #define AHCI_VERSION_1_20   0x00010200
  24 #define AHCI_VERSION_1_30   0x00010300
  25
  26 enum {
  27         CAP_S64A                = (1 << 31),    // Supports 64-bit Addressing
  28         CAP_SNCQ                = (1 << 30),    // Supports Native Command Queuing
  29         CAP_SSNTF               = (1 << 29),    // Supports SNotification Register
  30         CAP_SMPS                = (1 << 28),    // Supports Mechanical Presence Switch
  31         CAP_SSS                 = (1 << 27),    // Supports Staggered Spin-up
  32         CAP_SALP                = (1 << 26),    // Supports Aggressive Link Power Management
  33         CAP_SAL                 = (1 << 25),    // Supports Activity LED
  34         CAP_SCLO                = (1 << 24),    // Supports Command List Override
  35         CAP_ISS_MASK    = 0xf,                  // Interface Speed Support
  36         CAP_ISS_SHIFT   = 20,
  37         CAP_SNZO                = (1 << 19),    // Supports Non-Zero DMA Offsets
  38         CAP_SAM                 = (1 << 18),    // Supports AHCI mode only
  39         CAP_SPM                 = (1 << 17),    // Supports Port Multiplier
  40         CAP_FBSS                = (1 << 16),    // FIS-based Switching Supported
  41         CAP_PMD                 = (1 << 15),    // PIO Multiple DRQ Block
  42         CAP_SSC                 = (1 << 14),    // Slumber State Capable
  43         CAP_PSC                 = (1 << 13),    // Partial State Capable
  44         CAP_NCS_MASK    = 0x1f,                 // Number of Command Slots (zero-based number)
  45         CAP_NCS_SHIFT   = 8,
  46         CAP_CCCS                = (1 << 7),             // Command Completion Coalescing Supported
  47         CAP_EMS                 = (1 << 6),             // Enclosure Management Supported
  48         CAP_SXS                 = (1 << 5),     // Supports External SATA
  49         CAP_NP_MASK             = 0x1f,                 // Number of Ports (zero-based number)
  50         CAP_NP_SHIFT    = 0,
  51 };
  52
  53 enum {
  54     CAP2_APST       = (1 << 2),     // Automatic Partial to Slumber Transitions (APST)
  55     CAP2_NVNP       = (1 << 1),     // NVMHCI Present (NVMP)
  56     CAP2_BOH        = (1 << 0),     // BIOS/OS Handoff (BOH)
  57 };
  58
  59 enum {
  60     BOHC_BB         = (1 << 4),
  61     BOHC_OOC        = (1 << 3),
  62     BOHC_SOOE       = (1 << 2),
  63     BOHC_OOS        = (1 << 1),
  64     BOHC_BOS        = (1 << 0),
  65 };
  66
  67 enum {
  68         GHC_AE                  = (1 << 31),    // AHCI Enable
  69         GHC_MRSM                = (1 << 2),             // MSI Revert to Single Message
  70         GHC_IE                  = (1 << 1),             // Interrupt Enable
  71         GHC_HR                  = (1 << 0),             // HBA Reset **RW1**
  72 };
  73
  74 enum {
  75         PORT_CMD_ICC_ACTIVE      = (1 << 28),   // Interface Communication control
  76         PORT_CMD_ICC_SLUMBER = (6 << 28),       // Interface Communication control
  77         PORT_CMD_ICC_MASK    = (0xf<<28),       // Interface Communication control
  78         PORT_CMD_ATAPI  = (1 << 24),    // Device is ATAPI
  79         PORT_CMD_CR             = (1 << 15),    // Command List Running (DMA active)
  80         PORT_CMD_FR             = (1 << 14),    // FIS Receive Running
  81         PORT_CMD_FRE    = (1 << 4),             // FIS Receive Enable
  82         PORT_CMD_CLO    = (1 << 3),             // Command List Override
  83         PORT_CMD_POD    = (1 << 2),             // Power On Device
  84         PORT_CMD_SUD    = (1 << 1),             // Spin-up Device
  85         PORT_CMD_ST             = (1 << 0),             // Start DMA
  86 };
  87
  88 enum {
  89         PORT_INT_CPD    = (1 << 31),    // Cold Presence Detect Status/Enable
  90         PORT_INT_TFE    = (1 << 30),    // Task File Error Status/Enable
  91         PORT_INT_HBF    = (1 << 29),    // Host Bus Fatal Error Status/Enable
  92         PORT_INT_HBD    = (1 << 28),    // Host Bus Data Error Status/Enable
  93         PORT_INT_IF             = (1 << 27),    // Interface Fatal Error Status/Enable
  94         PORT_INT_INF    = (1 << 26),    // Interface Non-fatal Error Status/Enable
  95         PORT_INT_OF             = (1 << 24),    // Overflow Status/Enable
  96         PORT_INT_IPM    = (1 << 23),    // Incorrect Port Multiplier Status/Enable
  97         PORT_INT_PRC    = (1 << 22),    // PhyRdy Change Status/Enable
  98         PORT_INT_DI             = (1 << 7),             // Device Interlock Status/Enable
  99         PORT_INT_PC             = (1 << 6),             // Port Change Status/Enable
 100         PORT_INT_DP             = (1 << 5),             // Descriptor Processed Interrupt
 101         PORT_INT_UF             = (1 << 4),             // Unknown FIS Interrupt
 102         PORT_INT_SDB    = (1 << 3),             // Set Device Bits FIS Interrupt
 103         PORT_INT_DS             = (1 << 2),             // DMA Setup FIS Interrupt
 104         PORT_INT_PS             = (1 << 1),             // PIO Setup FIS Interrupt
 105         PORT_INT_DHR    = (1 << 0),             // Device to Host Register FIS Interrupt
 106 };
 107
 108 enum {
 109         PORT_TFD_ERR_MASK       = 0xff,         // Last error from task file
 110         PORT_TFD_ERR_SHIFT      = 8,
 111         PORT_TFD_STS_MASK       = 0xff,         // Status of task file
 112         PORT_TFD_STS_BSY        = (1 << 7),     // Busy
 113         PORT_TFD_STS_DRQ        = (1 << 3),     // Data requested
 114         PORT_TFD_STS_ERR        = (1 << 0),     // Transfer error
 115 };
 116
 117 enum {
 118         PORT_SIG_LBA_HIGH_MASK  = 0xff, // LBA High Register
 119         PORT_SIG_LBA_HIGH_SHIFT = 24,
 120         PORT_SIG_LBA_MED_MASK   = 0xff, // LBA Med Register
 121         PORT_SIG_LBA_MED_SHIFT  = 16,
 122         PORT_SIG_LBA_LOW_MASK   = 0xff, // LBA Low Register
 123         PORT_SIG_LBA_LOW_SHIFT  = 8,
 124         PORT_SIG_SECTORS_MASK   = 0xff, // Sector Count Register
 125 };
 126
 127 enum {
 128         PORT_SSTS_IPM_MASK      = (0xf << 8),   // Interface state
 129         PORT_SSTS_IPM_NODEV     = (0 << 8),     // No device present
 130         PORT_SSTS_IPM_ACTIVE    = (1 << 8),     // Interface active
 131         PORT_SSTS_IPM_PARTIAL   = (2 << 8),     // Partial power save
 132         PORT_SSTS_IPM_SLUMBER   = (6 << 8),     // Slumber power save
 133
 134         PORT_SSTS_SPD_MASK      = (0xf << 4),   // Interface speed
 135         PORT_SSTS_SPD_NODEV     = (0 << 4),     // Interface speed
 136         PORT_SSTS_SPD_GEN1      = (1 << 4),     // Interface speed
 137         PORT_SSTS_SPD_GEN2      = (2 << 4),     // Interface speed
 138         PORT_SSTS_SPD_GEN3      = (3 << 4),     // Interface speed
 139
 140         PORT_SSTS_DET_MASK      = 0xf,          // Device Detect
 141         PORT_SSTS_DET_NODEV     = (0 << 0),     // No device, no phy
 142         PORT_SSTS_DET_NOPHY     = (1 << 0),     // Device, but no phy
 143         PORT_SSTS_DET_ONLINE    = (3 << 0),     // Online and ready
 144         PORT_SSTS_DET_OFFLINE   = (4 << 0),     // Offline (Device in BIST?)
 145 };
 146
 147 enum {
 148         PORT_SERR_ERR_MASK      = 0xffff,       // Errors
 149 };
 150
 151 /********** DMAable Data Structures **********/
 152
 153 /* FIS RX structure
 154  * 256 bytes in size
 155  */
 156 struct ahci_fis {
 157     /* DMA setup FIS */
 158     union {
 159         struct dsfis {
 160         } dsfis;
 161         UBYTE dsfis_pad[0x20];
 162     };
 163
 164     /* PIO setup FIS */
 165     union {
 166         struct psfis {
 167         } psfis;
 168         UBYTE psfis_pad[0x20];
 169     };
 170
 171     /* D2H register FIS */
 172     union {
 173         struct rfis {
 174         } rfis;
 175         UBYTE rfis_pad[0x18];
 176     };
 177
 178     /* SetDevice FIS */
 179     union {
 180         struct sdbfis {
 181         } sdbfis;
 182         UBYTE sdbfis_pad[0x8];
 183     };
 184
 185     /* Unknown FIS */
 186     UBYTE ufis[0x40];
 187
 188     UBYTE resv[0x60];
 189 } __packed;
 190
 191 /* Command List Header Entry */
 192 struct ahci_cmdhdr {
 193     ULONG       cw0;    /* PRDTL, PMP, C, B, R, P, W, A, and CFL */
 194     ULONG       prdbc;  /* PRD byte count */
 195     ULONG       ctba;   /* Lower 32bits of the command table address. 128 byte aligned */
 196     ULONG       ctbu;   /* Uppoer 32bit of the command table address */
 197     ULONG       resv[4];
 198 } __packed;
 199
 200 enum {
 201     CW0_PRDTL_MASK      = 0xffff,  /* Physical Region Descriptor Table Length */
 202     CW0_PRDTL_SHIFT     = 16,
 203     CW0_PMP_MASK        = 0x1f,    /* Port Multiplier Port */
 204     CW0_PMP_SHIFT       = 12,
 205     CW0_C               = (1 << 10),    /* Clear Busy Upon R_OK */
 206     CW0_B               = (1 <<  9),    /* BIST */
 207     CW0_R               = (1 <<  8),    /* Reset */
 208     CW0_P               = (1 <<  7),    /* Prefetchable */
 209     CW0_W               = (1 <<  6),    /* Write to device */
 210     CW0_A               = (1 <<  5),    /* ATAPI */
 211     CW0_CFL_MASK        = 0x1f,         /* Command FIS Length in ULONGs. Max 16 */
 212 };
 213
 214 /* Command Table (pointed to by a command list header)
 215  * Must be 128 byte aligned.
 216  */
 217 struct ahci_cmdtab {
 218     /* Command FIS */
 219     union {
 220         struct cfis {
 221         } cfis;
 222         UBYTE pad_cfis[0x40];
 223     };
 224
 225     /* ATAPI Command */
 226     union {
 227         struct acmd {
 228         } acmd;
 229         UBYTE pad_acmd[0x10];
 230     };
 231
 232     UBYTE resv[0x30];
 233
 234     /* Physical Region Descriptor Table
 235      * (the scatter-gather DMA list)
 236      */
 237     struct prdt {
 238         ULONG   dba;    /* Data Base Address (USHORT aligned) */
 239         ULONG   dbau;   /* Data Base Upper 32 Address */
 240         ULONG   resv;   /* Reserved */
 241         ULONG   pw3;    /* I and DBC. See below. */
 242     } prdt[];   /* Up to 65535 entries allowed */
 243 } __packed;
 244
 245 enum {
 246     PW3_I          = (1 << 31), /* Interrupt on completion */
 247     PW3_DBC_MASK   = 0x3fffff,  /* N-1 bytes of transfer */
 248 };
 249
 250 struct ahci_hwport {
 251         volatile ULONG      clb;                        // Port x Command List Base Address (alignment 1024 byte)
 252         volatile ULONG      clbu;                       // Port x Command List Base Address Upper 32-Bits
 253         volatile ULONG      fb;                         // Port x FIS Base Address (alignment 256 byte)
 254         volatile ULONG      fbu;                        // Port x FIS Base Address Upper 32-Bits
 255         volatile ULONG      is;                         // Port x Interrupt Status
 256         volatile ULONG      ie;                         // Port x Interrupt Enable
 257         volatile ULONG      cmd;                        // Port x Command and Status
 258         volatile ULONG      res1;                       // Port x Reserved
 259         volatile ULONG      tfd;                        // Port x Task File Data
 260         volatile ULONG      sig;                        // Port x Signature
 261         volatile ULONG      ssts;                       // Port x Serial ATA Status (SCR0: SStatus)
 262         volatile ULONG      sctl;                       // Port x Serial ATA Control (SCR2: SControl)
 263         volatile ULONG      serr;                       // Port x Serial ATA Error (SCR1: SError)
 264         volatile ULONG      sact;                       // Port x Serial ATA Active (SCR3: SActive)
 265         volatile ULONG      ci;                         // Port x Command Issue
 266         volatile ULONG      sntf;                       // Port x Serial ATA Notification (SCR4: SNotification)
 267         volatile ULONG      res2;                       // Port x FIS-based Switching Control
 268         volatile ULONG      res[11];            // Port x Reserved
 269         volatile ULONG      vendor[4];          // Port x Vendor Specific
 270 } __packed;
 271
 272 struct ahci_hwhba {
 273     volatile ULONG      cap;                    // 0x00 Host Capabilities
 274     volatile ULONG      ghc;                    // 0x04 Global Host Control
 275     volatile ULONG      is;                             // 0x08 Interrupt Status
 276     volatile ULONG      pi;                             // 0x0c Ports Implemented
 277     volatile ULONG      vs;                             // 0x10 Version
 278     volatile ULONG      ccc_ctl;                // 0x14 Command Completion Coalescing Control
 279     volatile ULONG      ccc_ports;              // 0x18 Command Completion Coalsecing Ports
 280     volatile ULONG      em_loc;                 // 0x1c Enclosure Management Location
 281     volatile ULONG      em_ctl;                 // 0x20 Enclosure Management Control
 282     volatile ULONG      cap2;           // 0x24 Host Capabilities Extended
 283     volatile ULONG      bohc;           // 0x28 BIOS/OS Handoff Control and Status
 284     volatile ULONG      res[29];        // 0x2c-0x9f Reserved
 285     volatile ULONG      vendor[24];     // 0xa0-0xff Vendor Specific registers
 286     struct ahci_hwport  port[32];       // 0x100
 287 } __packed;
 288
 289 #endif // AHCI_HBA_H
 290
 291