arch/all-netbsd/kernel/cpu_i386.h

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef __AROS_EXEC_LIBRARY__
   7
   8 #include <signal.h>
   9
  10 typedef struct sigcontext regs_t;
  11 #define SIGHANDLER      bsd_sighandler
  12 #define SIGHANDLER_T    void *
  13
  14 #define SC_DISABLE(sc)   (sc->sc_mask = KernelBase->kb_PlatformData->sig_int_mask)
  15 #define SC_ENABLE(sc)    (pd->iface->SigEmptySet(&sc->sc_mask))
  16
  17 #define SP(sc)       (sc->sc_esp)
  18 #define FP(sc)       (sc->sc_ebp)
  19 #define PC(sc)       (sc->sc_eip)
  20
  21 #define R0(sc)           (sc->sc_eax)
  22 #define R1(sc)           (sc->sc_ebx)
  23 #define R2(sc)           (sc->sc_ecx)
  24 #define R3(sc)           (sc->sc_edx)
  25 #define R4(sc)           (sc->sc_edi)
  26 #define R5(sc)           (sc->sc_esi)
  27 #define R6(sc)           (sc->sc_eflags)
  28
  29 #define GLOBAL_SIGNAL_INIT(sighandler) \
  30         static void sighandler ## _gate (int sig, int code, struct sigcontext *sc) \
  31         {                                                    \
  32             sighandler( sig, (regs_t*)sc);       \
  33         }
  34
  35 #define SAVE_CPU(cc, sc)        \
  36     cc.eax    = R0(sc);         \
  37     cc.ebx    = R1(sc);         \
  38     cc.ecx    = R2(sc);         \
  39     cc.edx    = R3(sc);         \
  40     cc.edi    = R4(sc);         \
  41     cc.esi    = R5(sc);         \
  42     cc.eflags = R6(sc);         \
  43     cc.ebp    = FP(sc);         \
  44     cc.eip    = PC(sc);         \
  45     cc.esp    = SP(sc);         \
  46
  47 /*
  48  * Restore CPU registers.
  49  * Note that we do not restore segment registers because they
  50  * are of own use by the host OS.
  51  */
  52 #define RESTORE_CPU(cc, sc) \
  53     R0(sc) = cc.eax;        \
  54     R1(sc) = cc.ebx;        \
  55     R2(sc) = cc.ecx;        \
  56     R3(sc) = cc.edx;        \
  57     R4(sc) = cc.edi;        \
  58     R5(sc) = cc.esi;        \
  59     R6(sc) = cc.eflags;     \
  60     FP(sc) = cc.ebp;        \
  61     PC(sc) = cc.eip;        \
  62     SP(sc) = cc.esp;
  63
  64 /* TODO: FPU/SSE support */
  65
  66 #define SAVEREGS(ctx, sc)               \
  67     SAVE_CPU((ctx)->regs, sc);
  68
  69 #define RESTOREREGS(ctx, sc)            \
  70     RESTORE_CPU((ctx)->regs, sc);
  71
  72 #define PRINT_SC(sc) \
  73     bug("    SP=%08lx  FP=%08lx  PC=%08lx\n" \
  74         "    R0=%08lx  R1=%08lx  R2=%08lx  R3=%08lx\n" \
  75         "    R4=%08lx  R5=%08lx  R6=%08lx\n" \
  76         , SP(sc), FP(sc), PC(sc) \
  77         , R0(sc), R1(sc), R2(sc), R3(sc) \
  78         , R4(sc), R5(sc), R6(sc) \
  79         )
  80
  81 #endif /* __AROS_EXEC_LIBRARY__ */
  82
  83 #define EXCEPTIONS_COUNT 17
  84
  85 struct AROSCPUContext
  86 {
  87     struct ExceptionContext regs;
  88     int errno_backup;
  89 };