arch/all-darwin/kernel/cpu_i386.h

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <sys/types.h>
   7
   8 #include <aros/i386/cpucontext.h>
   9
  10 #ifdef __AROS_EXEC_LIBRARY__
  11
  12 /* regs_t is a black box here */
  13 struct ucontext;
  14 typedef struct ucontext *regs_t;
  15
  16 #else
  17
  18 #include <sys/ucontext.h>
  19
  20 #define SIGCORE_NEED_SA_SIGINFO
  21
  22 typedef ucontext_t regs_t;
  23
  24 #define SIGHANDLER      bsd_sighandler
  25 typedef void (*SIGHANDLER_T)(int);
  26
  27 #define SC_DISABLE(sc)   sc->uc_sigmask = KernelBase->kb_PlatformData->sig_int_mask
  28 #define SC_ENABLE(sc)    pd->iface->SigEmptySet(&(sc)->uc_sigmask)
  29
  30 /* work around silly renaming of struct members in OS X 10.5 */
  31 #if __DARWIN_UNIX03 && defined(_STRUCT_X86_EXCEPTION_STATE32)
  32
  33 #define R0(context)     ((context)->uc_mcontext->__ss.__eax)
  34 #define R1(context)     ((context)->uc_mcontext->__ss.__ebx)
  35 #define R2(context)     ((context)->uc_mcontext->__ss.__ecx)
  36 #define R3(context)     ((context)->uc_mcontext->__ss.__edx)
  37 #define R4(context)     ((context)->uc_mcontext->__ss.__edi)
  38 #define R5(context)     ((context)->uc_mcontext->__ss.__esi)
  39 #define R6(context)     ((context)->uc_mcontext->__ss.__eflags)
  40
  41 #define FP(context)     ((context)->uc_mcontext->__ss.__ebp)
  42 #define PC(context)     ((context)->uc_mcontext->__ss.__eip)
  43 #define SP(context)     ((context)->uc_mcontext->__ss.__esp)
  44
  45 #define SS(context)     ((context)->uc_mcontext->__ss.__ss)
  46 #define CS(context)     ((context)->uc_mcontext->__ss.__cs)
  47 #define DS(context)     ((context)->uc_mcontext->__ss.__ds)
  48 #define ES(context)     ((context)->uc_mcontext->__ss.__es)
  49 #define FS(context)     ((context)->uc_mcontext->__ss.__fs)
  50 #define GS(context)     ((context)->uc_mcontext->__ss.__gs)
  51
  52 #define FPSTATE(context) ((context)->uc_mcontext->__fs.__fpu_fcw)
  53
  54 #else
  55
  56 #define R0(context)     ((context)->uc_mcontext->ss.eax)
  57 #define R1(context)     ((context)->uc_mcontext->ss.ebx)
  58 #define R2(context)     ((context)->uc_mcontext->ss.ecx)
  59 #define R3(context)     ((context)->uc_mcontext->ss.edx)
  60 #define R4(context)     ((context)->uc_mcontext->ss.edi)
  61 #define R5(context)     ((context)->uc_mcontext->ss.esi)
  62 #define R6(context)     ((context)->uc_mcontext->ss.eflags)
  63
  64 #define FP(context)     ((context)->uc_mcontext->ss.ebp)
  65 #define PC(context)     ((context)->uc_mcontext->ss.eip)
  66 #define SP(context)     ((context)->uc_mcontext->ss.esp)
  67
  68 #define SS(context)     ((context)->uc_mcontext->ss.ss)
  69 #define CS(context)     ((context)->uc_mcontext->ss.cs)
  70 #define DS(context)     ((context)->uc_mcontext->ss.ds)
  71 #define ES(context)     ((context)->uc_mcontext->ss.es)
  72 #define FS(context)     ((context)->uc_mcontext->ss.fs)
  73 #define GS(context)     ((context)->uc_mcontext->ss.gs)
  74
  75 #define FPSTATE(context) ((context)->uc_mcontext->fs.fpu_fcw)
  76
  77 #endif
  78
  79 #define GLOBAL_SIGNAL_INIT(sighandler) \
  80         static void sighandler ## _gate (int sig, siginfo_t *info, void *sc) \
  81         {                                                    \
  82             sighandler(sig, sc);                             \
  83         }
  84
  85 #define SAVE_CPU(cc, sc)        \
  86     cc.Flags = ECF_SEGMENTS;    \
  87     cc.eax    = R0(sc);         \
  88     cc.ebx    = R1(sc);         \
  89     cc.ecx    = R2(sc);         \
  90     cc.edx    = R3(sc);         \
  91     cc.edi    = R4(sc);         \
  92     cc.esi    = R5(sc);         \
  93     cc.eflags = R6(sc);         \
  94     cc.ebp    = FP(sc);         \
  95     cc.eip    = PC(sc);         \
  96     cc.esp    = SP(sc);         \
  97     cc.cs     = CS(sc);         \
  98     cc.ds     = DS(sc);         \
  99     cc.es     = ES(sc);         \
 100     cc.fs     = FS(sc);         \
 101     cc.gs     = GS(sc);         \
 102     cc.ss     = SS(sc);
 103
 104 /*
 105  * Restore CPU registers.
 106  * Note that we do not restore segment registers because they
 107  * are of own use by Darwin.
 108  */
 109 #define RESTORE_CPU(cc, sc) \
 110     R0(sc) = cc.eax;        \
 111     R1(sc) = cc.ebx;        \
 112     R2(sc) = cc.ecx;        \
 113     R3(sc) = cc.edx;        \
 114     R4(sc) = cc.edi;        \
 115     R5(sc) = cc.esi;        \
 116     R6(sc) = cc.eflags;     \
 117     FP(sc) = cc.ebp;        \
 118     PC(sc) = cc.eip;        \
 119     SP(sc) = cc.esp;
 120
 121 /*
 122  * Save all registers from UNIX signal context ss to AROS context cc.
 123  * Saves SSE state only if the context has appropriate space for it.
 124  * Note that Darwin does not save legacy 8087 frame.
 125  */
 126 #define SAVEREGS(cc, sc)                                                                \
 127     SAVE_CPU((cc)->regs, sc);                                                           \
 128     if ((cc)->regs.FXData)                                                              \
 129     {                                                                                   \
 130         (cc)->regs.Flags |= ECF_FPX;                                                    \
 131         CopyMemQuick(&FPSTATE(sc), (cc)->regs.FXData, sizeof(struct FPXContext));       \
 132     }
 133
 134 /*
 135  * Restore all registers from AROS context to UNIX signal context.
 136  * Check context flags to decide whether to restore SSE or not.
 137  */
 138 #define RESTOREREGS(cc, sc)                                                             \
 139     RESTORE_CPU((cc)->regs, sc);                                                        \
 140     if ((cc)->regs.Flags & ECF_FPX)                                                     \
 141         CopyMemQuick((cc)->regs.FXData, &FPSTATE(sc), sizeof(struct FPXContext));
 142
 143 /* Print signal context. Used in crash handler. */
 144 #define PRINT_SC(sc) \
 145     bug ("    ESP=%08x  EBP=%08x  EIP=%08x\n" \
 146          "    EAX=%08x  EBX=%08x  ECX=%08x  EDX=%08x\n" \
 147          "    EDI=%08x  ESI=%08x  EFLAGS=%08x\n" \
 148             , SP(sc), FP(sc), PC(sc) \
 149             , R0(sc), R1(sc), R2(sc), R3(sc) \
 150             , R4(sc), R5(sc), R6(sc) \
 151         )
 152
 153 #endif /* __AROS_EXEC_LIBRARY__ */
 154
 155 #define EXCEPTIONS_COUNT 17
 156
 157 struct AROSCPUContext
 158 {
 159     struct ExceptionContext regs;
 160     int errno_backup;
 161 };