arch/i386-pc/exec/cachecleare.c

   1 /*
   2     Copyright © 1995-2008, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: CacheClearE() - Clear the caches with extended control.
   6     Lang: english
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/execbase.h>
  11 #include <aros/libcall.h>
  12
  13 void Exec_Wbinvd();
  14
  15 /*****************************************************************************
  16
  17     NAME */
  18 #include <proto/exec.h>
  19
  20         AROS_LH3(void, CacheClearE,
  21
  22 /*  SYNOPSIS */
  23         AROS_LHA(APTR, address, A0),
  24         AROS_LHA(ULONG, length, D0),
  25         AROS_LHA(ULONG, caches, D1),
  26
  27 /*  LOCATION */
  28         struct ExecBase *, SysBase, 107, Exec)
  29
  30 /*  FUNCTION
  31         Flush the contents of the CPU instruction or data caches. If some
  32         of the cache contains dirty data, push it to memory first.
  33
  34         For most systems DMA will not effect processor caches. If *any*
  35         external (non-processor) event changes system memory, you MUST
  36         clear the cache. For example:
  37
  38             DMA
  39             Code relocation to run at a different address
  40             Building jump tables
  41             Loading code from disk
  42
  43     INPUTS
  44         address -   Address to start the operation. This address may be
  45                     rounded DOWN due to hardware granularity.
  46         length  -   Length of the memory to flush. This will be rounded
  47                     up, of $FFFFFFFF to indicate that all addresses
  48                     should be cleared.
  49         caches  -   Bit flags to indicate which caches should be cleared
  50
  51                         CACRF_ClearI    -   Clear the instruction cache
  52                         CACRF_ClearD    -   Clear the data cache
  53
  54                     All other bits are reserved.
  55
  56     RESULT
  57         The caches will be flushed.
  58
  59     NOTES
  60         It is possible that on some systems the entire cache will be
  61         even if this was not the specific request.
  62
  63     EXAMPLE
  64
  65     BUGS
  66
  67     SEE ALSO
  68         CacheClearU(), CacheControl()
  69
  70     INTERNALS
  71     Due to the strong cache coherency of x86 systems this function
  72     is actually not needed. CPU snoops the address lines and
  73     invalidate all cache which is out-of-date. It is valid for both
  74     D and I caches). Even a BM-DMA transfer are perfectly safe here.
  75
  76 ******************************************************************************/
  77 {
  78     AROS_LIBFUNC_INIT
  79
  80     if (caches & CACRF_ClearD)
  81         Supervisor((ULONG_FUNC)Exec_Wbinvd);
  82
  83     AROS_LIBFUNC_EXIT
  84 } /* CacheClearE */
  85