workbench/devs/networks/atheros5000/hal/amigaos/ah_osdep.h

   1 /*
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  * $Id$
  18  */
  19 #ifndef _ATH_AH_OSDEP_H_
  20 #define _ATH_AH_OSDEP_H_
  21 /*
  22  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
  23  */
  24
  25 /*
  26  * Starting with 2.6.4 the kernel supports a configuration option
  27  * to pass parameters in registers.  If this is enabled we must
  28  * mark all function interfaces in+out of the HAL to pass parameters
  29  * on the stack as this is the convention used internally (for
  30  * maximum portability).
  31  */
  32 #define __ahdecl
  33 #ifndef __packed
  34 #define __packed        __attribute__((__packed__))
  35 #endif
  36
  37 /*
  38  * Beware of these being mismatched against the contents of <linux/types.h>
  39  */
  40 #ifndef _LINUX_TYPES_H
  41 /* NB: arm defaults to unsigned so be explicit */
  42 typedef signed char int8_t;
  43 typedef short int16_t;
  44 typedef int int32_t;
  45 typedef long long int64_t;
  46
  47 typedef unsigned char uint8_t;
  48 typedef unsigned short uint16_t;
  49 typedef unsigned int uint32_t;
  50 typedef unsigned long long uint64_t;
  51
  52 typedef unsigned int size_t;
  53 typedef unsigned int u_int;
  54 typedef void *va_list;
  55 #endif
  56
  57 /*
  58  * Linux/BSD gcc compatibility shims.
  59  */
  60 #define __printflike(_a,_b) \
  61         __attribute__ ((__format__ (__printf__, _a, _b)))
  62 #define __va_list       va_list
  63 #define OS_INLINE       __inline
  64
  65 /*
  66  * Delay n microseconds.
  67  */
  68 extern  void __ahdecl ath_hal_delay(int);
  69 #define OS_DELAY(_n)    ath_hal_delay(_n)
  70
  71 #define OS_MEMZERO(_a, _n)      ath_hal_memzero((_a), (_n))
  72 extern void __ahdecl ath_hal_memzero(void *, size_t);
  73 #define OS_MEMCPY(_d, _s, _n)   ath_hal_memcpy(_d,_s,_n)
  74 extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
  75
  76 #ifndef abs
  77 #define abs(_a)         __builtin_abs(_a)
  78 #endif
  79
  80 struct ath_hal;
  81 extern  uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
  82 #define OS_GETUPTIME(_ah)       ath_hal_getuptime(_ah)
  83
  84 /*
  85  * Byte order/swapping support.
  86  */
  87 #define AH_LITTLE_ENDIAN        1234
  88 #define AH_BIG_ENDIAN           4321
  89
  90 #ifndef AH_BYTE_ORDER
  91 /*
  92  * When the .inc file is not available (e.g. when building
  93  * in a kernel source tree); look for some other way to
  94  * setup the host byte order.
  95  */
  96 #ifdef __LITTLE_ENDIAN
  97 #define AH_BYTE_ORDER   AH_LITTLE_ENDIAN
  98 #endif
  99 #ifdef __BIG_ENDIAN
 100 #define AH_BYTE_ORDER   AH_BIG_ENDIAN
 101 #endif
 102 #define AH_BYTE_ORDER   AH_BIG_ENDIAN // !!!
 103 #ifndef AH_BYTE_ORDER
 104 #error "Do not know host byte order"
 105 #endif
 106 #endif /* AH_BYTE_ORDER */
 107
 108 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 109 /*
 110  * This could be optimized but since we only use it for
 111  * a few registers there's little reason to do so.
 112  */
 113 static __inline__ uint32_t
 114 __bswap32(uint32_t _x)
 115 {
 116         return ((uint32_t)(
 117               (((const uint8_t *)(&_x))[0]    ) |
 118               (((const uint8_t *)(&_x))[1]<< 8) |
 119               (((const uint8_t *)(&_x))[2]<<16) |
 120               (((const uint8_t *)(&_x))[3]<<24))
 121         );
 122 }
 123 #else
 124 #define __bswap32(_x)   (_x)
 125 #endif
 126
 127 /*
 128  * Register read/write; we assume the registers will always
 129  * be memory-mapped.  Note that register accesses are done
 130  * using target-specific functions when debugging is enabled
 131  * (AH_DEBUG) or we are explicitly configured this way.  The
 132  * latter is used on some platforms where the full i/o space
 133  * cannot be directly mapped.
 134  *
 135  * The hardware registers are native little-endian byte order.
 136  * Big-endian hosts are handled by enabling hardware byte-swap
 137  * of register reads and writes at reset.  But the PCI clock
 138  * domain registers are not byte swapped!  Thus, on big-endian
 139  * platforms we have to byte-swap those registers specifically.
 140  * Most of this code is collapsed at compile time because the
 141  * register values are constants.
 142  */
 143 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 144 #define OS_REG_UNSWAPPED(_reg) \
 145         (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
 146          ((_reg) >= 0x7000 && (_reg) < 0x8000))
 147 #define _OS_REG_WRITE(_ah, _reg, _val) do {                                 \
 148         if (OS_REG_UNSWAPPED(_reg))                                         \
 149                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) =           \
 150                         __bswap32((_val));                                  \
 151         else                                                                \
 152                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val);  \
 153 } while (0)
 154 #define _OS_REG_READ(_ah, _reg) \
 155         (OS_REG_UNSWAPPED(_reg) ? \
 156                 __bswap32(*((volatile uint32_t *)((_ah)->ah_sh + (_reg)))) : \
 157                 *((volatile uint32_t *)((_ah)->ah_sh + (_reg))))
 158 #else /* AH_LITTLE_ENDIAN */
 159 #define OS_REG_UNSWAPPED(_reg)  (0)
 160 #define _OS_REG_WRITE(_ah, _reg, _val) do { \
 161         *((volatile uint32_t *)((_ah)->ah_sh + (_reg))) = (_val); \
 162 } while (0)
 163 #define _OS_REG_READ(_ah, _reg) \
 164         *((volatile uint32_t *)((_ah)->ah_sh + (_reg)))
 165 #endif /* AH_BYTE_ORDER */
 166
 167 #if 0 && defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
 168 /* use functions to do register operations */
 169 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write(_ah, _reg, _val)
 170 #define OS_REG_READ(_ah, _reg)          ath_hal_reg_read(_ah, _reg)
 171
 172 extern  void __ahdecl ath_hal_reg_write(struct ath_hal *ah,
 173                 u_int reg, uint32_t val);
 174 extern  uint32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
 175 #else
 176 /* inline register operations */
 177 #define OS_REG_WRITE(_ah, _reg, _val)   _OS_REG_WRITE(_ah, _reg, _val)
 178 #define OS_REG_READ(_ah, _reg)          _OS_REG_READ(_ah, _reg)
 179 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
 180
 181 #ifdef AH_DEBUG_ALQ
 182 extern  void __ahdecl OS_MARK(struct ath_hal *, u_int id, uint32_t value);
 183 #else
 184 #define OS_MARK(_ah, _id, _v)
 185 #endif
 186
 187 #endif /* _ATH_AH_OSDEP_H_ */