arch/all-native/hidd/vga.hidd/vgahw.h

   1 #ifndef HIDD_VGAHW_H
   2 #define HIDD_VGAHW_H
   3
   4 /*
   5     Copyright © 1995-2001, The AROS Development Team. All rights reserved.
   6     $Id$
   7
   8     Desc: VGA hardwired.
   9     Lang: English.
  10 */
  11
  12 /* I have to move away this defines - should be in separate file */
  13
  14 #define inb(port) \
  15     ({  char __value;   \
  16         __asm__ __volatile__ ("inb %%dx,%%al":"=a"(__value):"d"(port)); \
  17         __value;        })
  18
  19 #define outb(port,val) \
  20     ({  char __value=(val);     \
  21         __asm__ __volatile__ ("outb %%al,%%dx"::"a"(__value),"d"(port)); })
  22
  23 #define inw(port) \
  24     ({  short __value;  \
  25         __asm__ __volatile__ ("inw %%dx,%%ax":"=a"(__value):"d"(port)); \
  26         __value;        })
  27
  28 #define outw(port,val) \
  29     ({  short __value=(val);    \
  30         __asm__ __volatile__ ("outw %%ax,%%dx"::"a"(__value),"d"(port)); })
  31
  32 #define inl(port) \
  33     ({  LONG __value;   \
  34         __asm__ __volatile__ ("inl %%dx,%%eax":"=a"(__value):"d"(port));        \
  35         __value;        })
  36
  37 #define outl(port,val) \
  38     ({  LONG __value=(val);     \
  39         __asm__ __volatile__ ("outl %%eax,%%dx"::"a"(__value),"d"(port)); })
  40
  41 #define DACDelay \
  42         { \
  43                 unsigned char temp = inb(vgaIOBase + 0x0A); \
  44                 temp = inb(vgaIOBase + 0x0A); \
  45         }
  46
  47 /* This structure keeps contents of mode registers including palette */
  48
  49 struct vgaHWRec
  50 {
  51   unsigned char MiscOutReg;     /* */
  52   unsigned char CRTC[25];       /* Crtc Controller */
  53   unsigned char Sequencer[5];   /* Video Sequencer */
  54   unsigned char Graphics[9];    /* Video Graphics */
  55   unsigned char Attribute[21];  /* Video Atribute */
  56   unsigned char DAC[768];       /* Internal Colorlookuptable */
  57   char NoClock;                 /* number of selected clock */
  58 };
  59
  60 /* CRT controller register indices */
  61
  62 #define CRTC_H_TOTAL        0
  63 #define CRTC_H_DISPLAY      1
  64 #define CRTC_H_BLANK_START  2
  65 #define CRTC_H_BLANK_END    3
  66 #define CRTC_H_SYNC_START   4
  67 #define CRTC_H_SYNC_END     5
  68 #define CRTC_V_TOTAL        6
  69 #define CRTC_OVERFLOW       7
  70 #define CRTC_PRESET_ROW     8
  71 #define CRTC_MAX_SCAN       9
  72 #define CRTC_CURSOR_START   10
  73 #define CRTC_CURSOR_END     11
  74 #define CRTC_START_HI       12
  75 #define CRTC_START_LO       13
  76 #define CRTC_CURSOR_HI      14
  77 #define CRTC_CURSOR_LO      15
  78 #define CRTC_V_SYNC_START   16
  79 #define CRTC_V_SYNC_END     17
  80 #define CRTC_V_DISP_END     18
  81 #define CRTC_OFFSET         19
  82 #define CRTC_UNDERLINE      20
  83 #define CRTC_V_BLANK_START  21
  84 #define CRTC_V_BLANK_END    22
  85 #define CRTC_MODE           23
  86 #define CRTC_LINE_COMPARE   24
  87
  88 #endif /* HIDD_VGAHW_H */