2 Copyright © 2014, The AROS Development Team. All rights reserved.
5 Desc: PCI XHCI USB host controller
15 #include <aros/debug.h>
16 #include <aros/macros.h>
17 #include <aros/asmcall.h>
18 #include <aros/symbolsets.h>
20 #include <proto/oop.h>
21 #include <proto/exec.h>
22 #include <proto/stdc.h>
23 #include <proto/arossupport.h>
25 #include <devices/usb.h>
26 #include <devices/usb_hub.h>
27 #include <devices/newstyle.h>
28 #include <devices/usbhardware.h>
34 #include <hidd/hidd.h>
36 #include "pcixhci_intern.h"
38 #include LC_LIBDEFS_FILE
40 #define PCIXHCIBase unit->pcixhcibase
42 VOID
PCIXHCI_PCIE(struct PCIXHCIUnit
*unit
) {
44 IPTR PCIE_CapO
, MSI_CapO
, MSIX_CapO
, PCIECap_SerialO
;
45 IPTR PCIE_Cap
=0 , MSI_Cap
=0 , MSIX_Cap
=0 , PCIECap_SerialL
=-1, PCIECap_SerialU
=-1;
47 OOP_GetAttr(unit
->hc
.pcidevice
, aHidd_PCIDevice_CapabilityPCIE
, (APTR
)&PCIE_CapO
);
48 OOP_GetAttr(unit
->hc
.pcidevice
, aHidd_PCIDevice_CapabilityMSIX
, (APTR
)&MSIX_CapO
);
49 OOP_GetAttr(unit
->hc
.pcidevice
, aHidd_PCIDevice_CapabilityMSI
, (APTR
)&MSI_CapO
);
50 OOP_GetAttr(unit
->hc
.pcidevice
, aHidd_PCIDevice_ExtendedCapabilitySerialNumber
, (APTR
)&PCIECap_SerialO
);
53 PCIE_Cap
= HIDD_PCIDevice_ReadConfigWord(unit
->hc
.pcidevice
, PCIE_CapO
+2);
56 MSIX_Cap
= HIDD_PCIDevice_ReadConfigWord(unit
->hc
.pcidevice
, MSIX_CapO
+2);
59 MSI_Cap
= HIDD_PCIDevice_ReadConfigWord(unit
->hc
.pcidevice
, MSI_CapO
+2);
62 PCIECap_SerialL
= HIDD_PCIDevice_ReadConfigLong(unit
->hc
.pcidevice
, PCIECap_SerialO
+4);
63 PCIECap_SerialU
= HIDD_PCIDevice_ReadConfigLong(unit
->hc
.pcidevice
, PCIECap_SerialO
+8);
66 mybug_unit(-1, ("\n"));
67 mybug_unit(-1, ("PCIECap_Serial %08x:%08x\n", PCIECap_SerialU
, PCIECap_SerialL
));
68 mybug_unit(-1, ("PCIE_Cap %08x\n", PCIE_Cap
));
69 mybug_unit(-1, ("MSIX_Cap %08x\n", MSIX_Cap
));
70 mybug_unit(-1, ("MSI_Cap %08x\n", MSI_Cap
));
72 mybug_unit(-1, ("\n"));