arch/ppc-chrp/exec/preparecontext.c

   1 #include <exec/types.h>
   2 #include <exec/execbase.h>
   3 #include <exec/memory.h>
   4 #include <utility/tagitem.h>
   5 #include <asm/mpc5200b.h>
   6 #include <proto/kernel.h>
   7
   8 #include "exec_intern.h"
   9 #include "exec_util.h"
  10
  11 #define DEBUG 0
  12
  13 #include <aros/libcall.h>
  14 #include <aros/debug.h>
  15
  16 BOOL PrepareContext(struct Task *task, APTR entryPoint, APTR fallBack,
  17                     const struct TagItem *tagList, struct ExecBase *SysBase)
  18 {
  19     context_t   *ctx;
  20     int         i;
  21     IPTR        *sp=(IPTR *)((IPTR)task->tc_SPReg & 0xfffffff0);
  22     IPTR        args[8] = {0};
  23     WORD        numargs = 0;
  24
  25     while(tagList)
  26     {
  27         switch(tagList->ti_Tag)
  28         {
  29             case TAG_MORE:
  30                 tagList = (const struct TagItem *)tagList->ti_Data;
  31                 continue;
  32
  33             case TAG_SKIP:
  34                 tagList += tagList->ti_Data;
  35                 break;
  36
  37             case TAG_DONE:
  38                 tagList = NULL;
  39                 break;
  40
  41             #define HANDLEARG(x) \
  42             case TASKTAG_ARG ## x: \
  43                 args[x - 1] = (IPTR)tagList->ti_Data; \
  44                 if (x > numargs) numargs = x; \
  45                 break;
  46
  47             HANDLEARG(1)
  48             HANDLEARG(2)
  49             HANDLEARG(3)
  50             HANDLEARG(4)
  51             HANDLEARG(5)
  52             HANDLEARG(6)
  53             HANDLEARG(7)
  54             HANDLEARG(8)
  55
  56             #undef HANDLEARG
  57             }
  58
  59         if (tagList) tagList++;
  60     }
  61
  62     if (!(task->tc_Flags & TF_ETASK) )
  63         return FALSE;
  64
  65     /* Get the memory for CPU context. Alloc it with MEMF_CLEAR flag */
  66     task->tc_UnionETask.tc_ETask->et_RegFrame = KrnCreateContext();
  67
  68     D(bug("[exec] PrepareContext: et_RegFrame = %012p\n", task->tc_UnionETask.tc_ETask->et_RegFrame));
  69
  70     if (!(ctx = (context_t *)task->tc_UnionETask.tc_ETask->et_RegFrame))
  71         return FALSE;
  72
  73     SuperState();
  74     if (numargs)
  75     {
  76         switch (numargs)
  77         {
  78             case 8:
  79                 ctx->cpu.gpr[10] = args[7];
  80             case 7:
  81                 ctx->cpu.gpr[9] = args[6];
  82             case 6:
  83                 ctx->cpu.gpr[8] = args[5];
  84             case 5:
  85                 ctx->cpu.gpr[7] = args[4];
  86             case 4:
  87                 ctx->cpu.gpr[6] = args[3];
  88             case 3:
  89                 ctx->cpu.gpr[5] = args[2];
  90             case 2:
  91                 ctx->cpu.gpr[4] = args[1];
  92             case 1:
  93                 ctx->cpu.gpr[3] = args[0];
  94                 break;
  95         }
  96     }
  97
  98     /* Push fallBack address */
  99     ctx->cpu.lr = fallBack;
 100     /*
 101      * Task will be started upon interrupt resume. Push entrypoint into SRR0
 102      * and the MSR register into SRR1. Enable FPU at the beginning
 103      */
 104     ctx->cpu.srr0 = (IPTR)entryPoint;
 105     ctx->cpu.srr1 = MSR_PR | MSR_EE | MSR_ME | MSR_IS | MSR_DS;
 106     ctx->cpu.srr1 |= MSR_FP;
 107     ctx->cpu.gpr[1] = sp;
 108
 109     task->tc_SPReg = sp;
 110
 111     sp[0] = 0;
 112     sp[1] = 0;
 113
 114     D(bug("[exec] New context:\n[exec] SRR0=%08x, SRR1=%08x\n",ctx->cpu.srr0, ctx->cpu.srr1));
 115     D(bug("[exec] GPR00=%08x GPR01=%08x GPR02=%08x GPR03=%08x\n",
 116              ctx->cpu.gpr[0],ctx->cpu.gpr[1],ctx->cpu.gpr[2],ctx->cpu.gpr[3]));
 117     D(bug("[exec] GPR04=%08x GPR05=%08x GPR06=%08x GPR07=%08x\n",
 118              ctx->cpu.gpr[4],ctx->cpu.gpr[5],ctx->cpu.gpr[6],ctx->cpu.gpr[7]));
 119     D(bug("[exec] GPR08=%08x GPR09=%08x GPR10=%08x GPR11=%08x\n",
 120              ctx->cpu.gpr[8],ctx->cpu.gpr[9],ctx->cpu.gpr[10],ctx->cpu.gpr[11]));
 121     D(bug("[exec] GPR12=%08x GPR13=%08x GPR14=%08x GPR15=%08x\n",
 122              ctx->cpu.gpr[12],ctx->cpu.gpr[13],ctx->cpu.gpr[14],ctx->cpu.gpr[15]));
 123
 124     D(bug("[exec] GPR16=%08x GPR17=%08x GPR18=%08x GPR19=%08x\n",
 125              ctx->cpu.gpr[16],ctx->cpu.gpr[17],ctx->cpu.gpr[18],ctx->cpu.gpr[19]));
 126     D(bug("[exec] GPR20=%08x GPR21=%08x GPR22=%08x GPR23=%08x\n",
 127              ctx->cpu.gpr[20],ctx->cpu.gpr[21],ctx->cpu.gpr[22],ctx->cpu.gpr[23]));
 128     D(bug("[exec] GPR24=%08x GPR25=%08x GPR26=%08x GPR27=%08x\n",
 129              ctx->cpu.gpr[24],ctx->cpu.gpr[25],ctx->cpu.gpr[26],ctx->cpu.gpr[27]));
 130     D(bug("[exec] GPR28=%08x GPR29=%08x GPR30=%08x GPR31=%08x\n",
 131              ctx->cpu.gpr[28],ctx->cpu.gpr[29],ctx->cpu.gpr[30],ctx->cpu.gpr[31]));
 132
 133     UserState(NULL);
 134
 135     return TRUE;
 136 }