2 #include <aros/m68k/asm.h>
3 #include <aros/config.h>
12 bra.w arosbootstrap_init
16 /* Wait a bit for reset to finish.
17 * Simulate ROM checksum check.
28 /* Check for cartridge ROM */
30 move.w %a0@(0),%d0 /* Get the ROM ID (0x1111) */
32 bne.s 0f /* Must be 0x1111 */
37 beq.s 0f /* skip if we booted at 0xF00000 */
38 lea 0x40000,%sp /* Safe stack at Chip Mem 128K */
43 /* Disable the overlay, power led off. */
51 /* Initial Custom chipset setup. Does same writes as AOS.
52 * It is possible some bus snooping hardware assumes this.
56 move.w %d0,0x9a(%a0) /* Interrupt disable */
57 move.w %d0,0x9c(%a0) /* Clear interrupts */
58 move.w %d0,0x96(%a0) /* Stop DMA */
59 move.w #0x0174,0x032(%a0) /* SERPER */
60 move.w #0x0200,0x100(%a0) /* BPLCON0 */
61 move.w #0x0000,0x110(%a0) /* BPL1DAT */
62 move.w #0x0111,0x180(%a0) /* COLOR00 */
64 /* temp system stack */
65 lea.l _ss_end,%sp /* System stack */
66 /* Put the memory bank array at the bottom of the stack, reserve space for extra memory bank */
69 /* Do we have a Gayle? */
71 jsr AROS_SLIB_ENTRY(ReadGayle,Exec,136)
76 /* Disable PCMCIA slot */
81 move.l %a5,%a4 /* Space for CPU/FPU data array */
82 lea 16(%a5),%a5 /* Space also reserved for extra membank */
85 /* High word = gayle flag, low word = AttnFlags */
88 btst #2,%d6 /* AttnFlags AFB_68030? */
90 btst #1,%d6 /* AttnFlags AFB_68020? */
92 /* 32-bit CPU check only, no memory tested */
93 move.l #0x08000000,%a0
94 move.l #0x08000000,%a1
95 move.l #0x00100000,%d0
99 /* set AttnFlags AFB_ADDR32 */
103 /* Memory region array is put into the
104 * system stack from the bottom up, so
105 * we check the non-autoconfig memory areas
106 * in order of fastest to slowest, going
107 * up the system stack in A5.
111 move.l #0x00c00000,%a0
112 move.l #0x00d80000,%a1
113 /* Limit max size if Gayle */
116 move.l #0x00dc0000,%a1
117 0: move.l #0x00040000,%d0
122 move.l #0x00200000,%a1
123 move.l #0x00040000,%d0
127 /* end of memory region list */
132 move.l %a5,%sp@- /* CPU/FPU data array */
134 move.l %a5,%sp@- /* memory bank array */
138 move.w #0x0f0,0xdff180
145 movem.l %d2-%d5/%a2-%a3/%a5,%sp@-
146 move.w 0xdff01c,%sp@- /* save INTENA */
153 move.w %d1,0xdff09a /* restore INTENA */
154 movem.l %sp@+,%d2-%d5/%a2-%a3/%a5
157 /******** Memory tester *******/
158 * IN: A0 - Address, A1 - Max end address, A5 - outtable
159 * IN: D0 = block size
160 * OUT: D0 - Detected size
161 * TRASH: D1, D2, D3, D4, D5, A1, A2, A3
165 move.l %a0,%a5@ /* write start address */
167 sub.l %a0,%d0 /* max size */
170 and.l #0xff000000,%d1
171 beq.s .L_memtest_24bitaddr
172 /* test if 32bit address mirrors address zero */
174 move.l 0.w,%d2 /* save old */
176 move.l #0xfecaf00d,%d1
180 move.l %d1,0x100.w /* write something else, some bus types "remember" old value */
182 nop /* force 68040/060 bus cycle to finish */
184 bne.s .L_memtest_32bitok /* different? no mirror */
185 move.l #0xcafed00d,%d1
193 bne.s .L_memtest_32bitok /* check again, maybe 0 already had our test value */
194 move.l %d2,0.w /* restore saved value */
197 bra .L_memtest_none /* 24-bit CPU, do not test this range */
199 move.l %d2,0.w /* restore saved value */
201 .L_memtest_24bitaddr:
203 /* a0 = tested address, d0 = max size, d1 = current size */
211 and.l #0xff000000,%d2
212 bne.s .L_memtest_chipcheck_done /* no chiptest if 32bit address */
213 move.w #0x7fff,0xdff09a
215 tst.w %a0@(0x1c,%d1) /* If non-zero, this is not INTENAR */
216 bne.s .L_memtest_chipcheck_done
217 /* It was zero ... */
218 move.w #0xc000,0xdff09a /* Try the master enable */
220 tst.w %a0@(0x1c,%d1) /* If still zero, not INTENAR */
221 bne .L_memtest_done /* It was a custom chip. */
222 .L_memtest_chipcheck_done:
226 cmp.l #.L_memtest,%a2 /* Make sure we don't modify our own test code */
227 bcs.s .L_memtest_nottestcode
228 cmp.l #.L_memtest_end,%a2
229 bcs.s .L_memtest_next
230 .L_memtest_nottestcode:
232 move.l %a0@(%d1),%d3 /* read old value */
233 move.l %a0@,%a2 /* save mirror test contents */
234 move.l #0xfecaf00d,%a0@ /* write mirror test value */
236 move.l #0xcafed00d,%d2
237 move.l %d2,%a0@(%d1) /* write test pattern */
239 tst.l %d1 /* first test addrress? */
240 beq.s .L_memtest_nomirror
241 cmp.l %a0@,%d2 /* no, check mirrorirng */
242 bne.s .L_memtest_nomirror
243 move.l %a2,%a0@ /* restore mirror test contents */
244 bra.s .L_memtest_done
248 move.l %a0@(4,%d1),%a3 /* read temp address */
249 move.l %d2,%a0@(4,%d1) /* fill bus with something else */
252 move.l %a0@(%d1),%d4 /* read test pattern */
253 move.l %a3,%a0@(4,%d1) /* restore */
255 cmp.l %d4,%d2 /* pattern match? */
256 bne.s .L_memtest_done
257 neg.l %d2 /* test pattern 2 */
259 move.l %d2,%a0@(%d1) /* write test pattern */
262 move.l %a0@(4,%d1),%a3 /* read temp address */
263 move.l %d2,%a0@(4,%d1) /* fill bus with something else */
266 move.l %a0@(%d1),%d4 /* read test pattern */
267 move.l %a3,%a0@(4,%d1) /* restore */
270 bne.s .L_memtest_done
272 move.l %d3,%a0@(%d1) /* write old value back */
274 move.l %a2,%a0@ /* restore mirror test contents */
276 add.l %d5,%d1 /* next block */
280 tst.l %d1 /* nothing found? */
281 beq.s .L_memtest_none
289 #define STACK_OFFSET (6*4)
290 .globl Early_Exception
293 #if AROS_SERIAL_DEBUG
294 movem.l %d0-%d2/%a0-%a2,-(%sp)
298 move.l STACK_OFFSET+2(%sp),-(%sp)
304 move.w STACK_OFFSET+6(%sp),%d0
310 move.l STACK_OFFSET+8(%sp),-(%sp)
315 movem.l (%sp)+,%d0-%d2/%a0-%a2
317 jmp Early_TrapHandler
321 .string "Early Exception!\nPC"