arch/arm-native/soc/broadcom/2708/include/hardware/bcm2708.h

   1 /*
   2     Copyright © 2013-2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef BCM2708_H
   7 #define BCM2708_H
   8
   9 #define CLID_I2C_BCM2708                                "hidd.i2c.bcm2708"
  10
  11 #define BCM2835_PERIPHYSBASE                            0x20000000                      // Peripheral physical base address
  12 #define BCM2836_PERIPHYSBASE                            0x3f000000                       // Peripheral physical base address
  13 #define BCM2708_PERIPHYSSIZE                            0x1000000
  14 #define BCM2835_PERIBUSBASE                             0x7E000000
  15
  16 #define BCM_BUSBASE                                     BCM2835_PERIBUSBASE
  17 #define ARM_PERIIOSIZE                                  BCM2708_PERIPHYSSIZE
  18
  19 #if (1)
  20 // TODO: Move to a more generic ARM header..
  21 #define ARM_VIRTBASE                                    0xF0000000
  22 #define ARM_PRIMECELLID                                 0xB105F00D
  23 #define ARM_PRIMECELLPERISIZE                           0x1000
  24 #endif
  25
  26 /*
  27    caller must provide ARM_PERIIOBASE
  28 */
  29
  30 #define SYSTIMER_BASE                                   (ARM_PERIIOBASE + 0x003000)
  31 #define ARMTIMER_BASE                                   (ARM_PERIIOBASE + 0x00b000)
  32 #define IRQ_BASE                                        (ARM_PERIIOBASE + 0x00b200)
  33 #define GPIO_PADS                                       (ARM_PERIIOBASE + 0x100000)
  34 #define CLOCK_BASE                                      (ARM_PERIIOBASE + 0x101000)
  35 #define GPIO_BASE                                       (ARM_PERIIOBASE + 0x200000)
  36
  37 #define SPI0_BASE                                       (ARM_PERIIOBASE + 0x204000)
  38 #define BSC0_BASE                                       (ARM_PERIIOBASE + 0x205000)
  39 #define GPIO_PWM                                        (ARM_PERIIOBASE + 0x20C000)
  40 #define V3D_BASE                                        (ARM_PERIIOBASE + 0xc00000)
  41
  42 #define SYSTIMER_CS                                     (SYSTIMER_BASE + 0x00)
  43 #define SYSTIMER_CLO                                    (SYSTIMER_BASE + 0x04)
  44 #define SYSTIMER_CHI                                    (SYSTIMER_BASE + 0x08)
  45 #define SYSTIMER_C0                                     (SYSTIMER_BASE + 0x0c)
  46 #define SYSTIMER_C1                                     (SYSTIMER_BASE + 0x10)
  47 #define SYSTIMER_C2                                     (SYSTIMER_BASE + 0x14)
  48 #define SYSTIMER_C3                                     (SYSTIMER_BASE + 0x18)
  49
  50 #define SYSTIMER_M0                                     (1 << 0)
  51 #define SYSTIMER_M1                                     (1 << 1)
  52 #define SYSTIMER_M2                                     (1 << 2)
  53 #define SYSTIMER_M3                                     (1 << 3)
  54
  55 #define ARMTIMER_LOAD                                   (ARMTIMER_BASE + 0x400)
  56 #define ARMTIMER_VALUE                                  (ARMTIMER_BASE + 0x404)
  57 #define ARMTIMER_CONTROL                                (ARMTIMER_BASE + 0x408)
  58 #define ARMTIMER_IRQ_ACK                                (ARMTIMER_BASE + 0x40c)
  59 #define ARMTIMER_IRQ_RAW                                (ARMTIMER_BASE + 0x410)
  60 #define ARMTIMER_IRQ_MSK                                (ARMTIMER_BASE + 0x414)
  61 #define ARMTIMER_RELOAD                                 (ARMTIMER_BASE + 0x418)
  62 #define ARMTIMER_PREDIV                                 (ARMTIMER_BASE + 0x41c)
  63 #define ARMTIMER_FRC                                    (ARMTIMER_BASE + 0x420)
  64
  65 #define ARMIRQ_PEND                                     (IRQ_BASE + 0x00)
  66 #define GPUIRQ_PEND0                                    (IRQ_BASE + 0x04)               // Pending IRQs
  67 #define GPUIRQ_PEND1                                    (IRQ_BASE + 0x08)
  68 #define GPUIRQ_ENBL0                                    (IRQ_BASE + 0x10)               // IRQ enable bits
  69 #define GPUIRQ_ENBL1                                    (IRQ_BASE + 0x14)
  70 #define ARMIRQ_ENBL                                     (IRQ_BASE + 0x18)
  71 #define GPUIRQ_DIBL0                                    (IRQ_BASE + 0x1C)               // IRQ disable bits
  72 #define GPUIRQ_DIBL1                                    (IRQ_BASE + 0x20)
  73 #define ARMIRQ_DIBL                                     (IRQ_BASE + 0x24)
  74
  75 #define IRQ_MASK(irq)                                   (1 << (irq & 0x1f))
  76 #define IRQ_BANK(irq)                                   (irq >> 5)
  77
  78 #define GPUIRQ0_BASE                                    (0 << 5)
  79 #define IRQ_TIMER0                                      (GPUIRQ0_BASE + 0)
  80 #define IRQ_TIMER1                                      (GPUIRQ0_BASE + 1)
  81 #define IRQ_TIMER2                                      (GPUIRQ0_BASE + 2)
  82 #define IRQ_TIMER3                                      (GPUIRQ0_BASE + 3)
  83 #define IRQ_CODEC0                                      (GPUIRQ0_BASE + 4)
  84 #define IRQ_CODEC1                                      (GPUIRQ0_BASE + 5)
  85 #define IRQ_CODEC2                                      (GPUIRQ0_BASE + 6)
  86 #define IRQ_VC_JPEG                                     (GPUIRQ0_BASE + 7)
  87 #define IRQ_ISP                                         (GPUIRQ0_BASE + 8)
  88 #define IRQ_VC_USB                                      (GPUIRQ0_BASE + 9)
  89 #define IRQ_VC_3D                                       (GPUIRQ0_BASE + 10)
  90 #define IRQ_TRANSPOSER                                  (GPUIRQ0_BASE + 11)
  91 #define IRQ_MULTICORESYNC0                              (GPUIRQ0_BASE + 12)
  92 #define IRQ_MULTICORESYNC1                              (GPUIRQ0_BASE + 13)
  93 #define IRQ_MULTICORESYNC2                              (GPUIRQ0_BASE + 14)
  94 #define IRQ_MULTICORESYNC3                              (GPUIRQ0_BASE + 15)
  95 #define IRQ_DMA0                                        (GPUIRQ0_BASE + 16)
  96 #define IRQ_DMA1                                        (GPUIRQ0_BASE + 17)
  97 #define IRQ_VC_DMA2                                     (GPUIRQ0_BASE + 18)
  98 #define IRQ_VC_DMA3                                     (GPUIRQ0_BASE + 19)
  99 #define IRQ_DMA4                                        (GPUIRQ0_BASE + 20)
 100 #define IRQ_DMA5                                        (GPUIRQ0_BASE + 21)
 101 #define IRQ_DMA6                                        (GPUIRQ0_BASE + 22)
 102 #define IRQ_DMA7                                        (GPUIRQ0_BASE + 23)
 103 #define IRQ_DMA8                                        (GPUIRQ0_BASE + 24)
 104 #define IRQ_DMA9                                        (GPUIRQ0_BASE + 25)
 105 #define IRQ_DMA10                                       (GPUIRQ0_BASE + 26)
 106 #define IRQ_DMA11                                       (GPUIRQ0_BASE + 27)
 107 #define IRQ_DMA12                                       (GPUIRQ0_BASE + 28)
 108 #define IRQ_AUX                                         (GPUIRQ0_BASE + 29)
 109 #define IRQ_ARM                                         (GPUIRQ0_BASE + 30)
 110 #define IRQ_VPUDMA                                      (GPUIRQ0_BASE + 31)
 111
 112 #define GPUIRQ1_BASE                                    (1 << 5)
 113 #define IRQ_HOSTPORT                                    (GPUIRQ1_BASE + 0)
 114 #define IRQ_VIDEOSCALER                                 (GPUIRQ1_BASE + 1)
 115 #define IRQ_CCP2TX                                      (GPUIRQ1_BASE + 2)
 116 #define IRQ_SDC                                         (GPUIRQ1_BASE + 3)
 117 #define IRQ_DSI0                                        (GPUIRQ1_BASE + 4)
 118 #define IRQ_AVE                                         (GPUIRQ1_BASE + 5)
 119 #define IRQ_CAM0                                        (GPUIRQ1_BASE + 6)
 120 #define IRQ_CAM1                                        (GPUIRQ1_BASE + 7)
 121 #define IRQ_HDMI0                                       (GPUIRQ1_BASE + 8)
 122 #define IRQ_HDMI1                                       (GPUIRQ1_BASE + 9)
 123 #define IRQ_PIXELVALVE1                                 (GPUIRQ1_BASE + 10)
 124 #define IRQ_I2CSPISLV                                   (GPUIRQ1_BASE + 11)
 125 #define IRQ_DSI1                                        (GPUIRQ1_BASE + 12)
 126 #define IRQ_PWA0                                        (GPUIRQ1_BASE + 13)
 127 #define IRQ_PWA1                                        (GPUIRQ1_BASE + 14)
 128 #define IRQ_CPR                                         (GPUIRQ1_BASE + 15)
 129 #define IRQ_SMI                                         (GPUIRQ1_BASE + 16)
 130 #define IRQ_GPIO0                                       (GPUIRQ1_BASE + 17)
 131 #define IRQ_GPIO1                                       (GPUIRQ1_BASE + 18)
 132 #define IRQ_GPIO2                                       (GPUIRQ1_BASE + 19)
 133 #define IRQ_GPIO3                                       (GPUIRQ1_BASE + 20)
 134 #define IRQ_VC_I2C                                      (GPUIRQ1_BASE + 21)
 135 #define IRQ_VC_SPI                                      (GPUIRQ1_BASE + 22)
 136 #define IRQ_VC_I2SPCM                                   (GPUIRQ1_BASE + 23)
 137 #define IRQ_VC_SDIO                                     (GPUIRQ1_BASE + 24)
 138 #define IRQ_VC_UART                                     (GPUIRQ1_BASE + 25)
 139 #define IRQ_SLIMBUS                                     (GPUIRQ1_BASE + 26)
 140 #define IRQ_VEC                                         (GPUIRQ1_BASE + 27)
 141 #define IRQ_CPG                                         (GPUIRQ1_BASE + 28)
 142 #define IRQ_RNG                                         (GPUIRQ1_BASE + 29)
 143 #define IRQ_VC_ARASANSDIO                               (GPUIRQ1_BASE + 30)
 144 #define IRQ_AVSPMON                                     (GPUIRQ1_BASE + 31)
 145
 146 #define ARMIRQ_BASE                                     (2 << 5)
 147 #define IRQ_ARM_TIMER                                   (ARMIRQ_BASE + 0)
 148 #define IRQ_ARM_MAILBOX                                 (ARMIRQ_BASE + 1)
 149 #define IRQ_ARM_DOORBELL_0                              (ARMIRQ_BASE + 2)
 150 #define IRQ_ARM_DOORBELL_1                              (ARMIRQ_BASE + 3)
 151 #define IRQ_VPU0_HALTED                                 (ARMIRQ_BASE + 4)
 152 #define IRQ_VPU1_HALTED                                 (ARMIRQ_BASE + 5)
 153 #define IRQ_ILLEGAL_TYPE0                               (ARMIRQ_BASE + 6)
 154 #define IRQ_ILLEGAL_TYPE1                               (ARMIRQ_BASE + 7)
 155 #define IRQ_PENDING1                                    (ARMIRQ_BASE + 8)
 156 #define IRQ_PENDING2                                    (ARMIRQ_BASE + 9)
 157
 158 #define GPIO_PADS_0_27                                  0x002c
 159 #define GPIO_PADS_28_45                                 0x0030
 160 #define GPIO_PADS_46_53                                 0x0034
 161
 162 #define GPFSEL0                                         (GPIO_BASE + 0x0)               // GPIO Function Selectors..
 163 #define GPFSEL1                                         (GPIO_BASE + 0x4)
 164 #define GPFSEL2                                         (GPIO_BASE + 0x8)
 165 #define GPFSEL3                                         (GPIO_BASE + 0xC)
 166 #define GPFSEL4                                         (GPIO_BASE + 0x10)
 167 #define GPFSEL5                                         (GPIO_BASE + 0x14)
 168 #define GPSET0                                          (GPIO_BASE + 0x1C)              // GPIO Pin Output control..
 169 #define GPSET1                                          (GPIO_BASE + 0x20)
 170 #define GPCLR0                                          (GPIO_BASE + 0x28)
 171 #define GPCLR1                                          (GPIO_BASE + 0x2C)
 172 #define GPLEV0                                          (GPIO_BASE + 0x34)              // GPIO Pin Levels..
 173 #define GPLEV1                                          (GPIO_BASE + 0x38)
 174 #define GPEDS0                                          (GPIO_BASE + 0x40)              // GPIO Pin Event Detect Status ..
 175 #define GPEDS1                                          (GPIO_BASE + 0x44)
 176 #define GPREN0                                          (GPIO_BASE + 0x4C)              // GPIO Pin Rising Edge Detect Enables..
 177 #define GPREN1                                          (GPIO_BASE + 0x50)
 178 #define GPFEN0                                          (GPIO_BASE + 0x58)              // GPIO Pin Falling Edge Detect Enables..
 179 #define GPFEN1                                          (GPIO_BASE + 0x5C)
 180 #define GPHEN0                                          (GPIO_BASE + 0x64)
 181 #define GPHEN1                                          (GPIO_BASE + 0x68)
 182 #define GPLEN0                                          (GPIO_BASE + 0x70)
 183 #define GPLEN1                                          (GPIO_BASE + 0x74)
 184 #define GPAREN0                                         (GPIO_BASE + 0x7c)
 185 #define GPAREN1                                         (GPIO_BASE + 0x80)
 186 #define GPAFEN0                                         (GPIO_BASE + 0x88)
 187 #define GPAFEN1                                         (GPIO_BASE + 0x8c)
 188 #define GPPUD                                           (GPIO_BASE + 0x94)
 189 #define GPPUDCLK0                                       (GPIO_BASE + 0x98)
 190 #define GPPUDCLK1                                       (GPIO_BASE + 0x9c)
 191
 192 #define SPI0_CS                                         (0x00)
 193 #define SPI0_FIFO                                       (0x04)
 194 #define SPI0_CLK                                        (0x08)
 195 #define SPI0_DLEN                                       (0x0c)
 196 #define SPI0_LTOH                                       (0x10)
 197 #define SPI0_DC                                         (0x14)
 198
 199 #define BSC0_CONTROL                                    (BSC0_BASE + 0x00)
 200 #define BSC0_STATUS                                     (BSC0_BASE + 0x01)
 201 #define BSC0_DATALEN                                    (BSC0_BASE + 0x02)
 202 #define BSC0_FIFO                                       (BSC0_BASE + 0x04)
 203
 204 #define BSC_CONTROL_READ                                (1 << 0)
 205 #define BSC_CONTROL_CLEAR                               (1 << 4)
 206 #define BSC_CONTROL_ST                                  (1 << 7)
 207 #define BSC_CONTROL_INTD                                (1 << 8)
 208 #define BSC_CONTROL_INTT                                (1 << 9)
 209 #define BSC_CONTROL_INTR                                (1 << 10)
 210 #define BSC_CONTROL_I2CEN                               (1 << 15)
 211
 212 #define BSC_STATUS_TA                                   (1 << 0)
 213 #define BSC_STATUS_DONE                                 (1 << 1)
 214 #define BSC_STATUS_TXW                                  (1 << 2)
 215 #define BSC_STATUS_RXR                                  (1 << 3)
 216 #define BSC_STATUS_TXD                                  (1 << 4)
 217 #define BSC_STATUS_RXD                                  (1 << 5)
 218 #define BSC_STATUS_TXE                                  (1 << 6)
 219 #define BSC_STATUS_RXF                                  (1 << 7)
 220 #define BSC_STATUS_ERR                                  (1 << 8)
 221 #define BSC_STATUS_CLKT                                 (1 << 9)
 222
 223 #define BSC_READ                                        BSC_CONTROL_I2CEN|BSC_CONTROL_ST|BSC_CONTROL_CLEAR|BSC_CONTROL_READ
 224 #define BSC_WRITE                                       BSC_CONTROL_I2CEN|BSC_CONTROL_ST
 225 #define BSC_CLEAR                                       BSC_STATUS_CLKT|BSC_STATUS_ERR|BSC_STATUS_DONE
 226
 227 #define AUX_IRQ                                         (ARM_PERIIOBASE + 0x215000)       // Auxiliary Interrupt status
 228 #define AUX_ENABLES                                     (ARM_PERIIOBASE + 0x215004)       // Auxiliary enables
 229 #define AUX_MU_IO_REG                                   (ARM_PERIIOBASE + 0x215040)       // AUX_MU_IO_REG Mini Uart I/O Data
 230 #define AUX_MU_IER_REG                                  (ARM_PERIIOBASE + 0x215044)       // Mini Uart Interrupt Enable
 231 #define AUX_MU_IIR_REG                                  (ARM_PERIIOBASE + 0x215048)       // Mini Uart Interrupt Identify
 232 #define AUX_MU_LCR_REG                                  (ARM_PERIIOBASE + 0x21504C)       // Mini Uart Line Control
 233 #define AUX_MU_MCR_REG                                  (ARM_PERIIOBASE + 0x215050)       // Mini Uart Modem Control
 234 #define AUX_MU_LSR_REG                                  (ARM_PERIIOBASE + 0x215054)       // Mini Uart Line Status
 235 #define AUX_MU_MSR_REG                                  (ARM_PERIIOBASE + 0x215058)       // Mini Uart Modem Status
 236 #define AUX_MU_SCRATCH                                  (ARM_PERIIOBASE + 0x21505C)       // Mini Uart Scratch
 237 #define AUX_MU_CNTL_REG                                 (ARM_PERIIOBASE + 0x215060)       // Mini Uart Extra Control
 238 #define AUX_MU_STAT_REG                                 (ARM_PERIIOBASE + 0x215064)       // Mini Uart Extra Status
 239 #define AUX_MU_BAUD_REG                                 (ARM_PERIIOBASE + 0x215068)       // Mini Uart Baudrate
 240 #define AUX_SPI0_CNTL0_REG                              (ARM_PERIIOBASE + 0x215080)       // SPI 1 Control register 0
 241 #define AUX_SPI0_CNTL1_REG                              (ARM_PERIIOBASE + 0x215084)       // SPI 1 Control register 1
 242 #define AUX_SPI0_STAT_REG                               (ARM_PERIIOBASE + 0x215088)       // SPI 1 Status
 243 #define AUX_SPI0_IO_REG                                 (ARM_PERIIOBASE + 0x215090)       // SPI 1 Data
 244 #define AUX_SPI0_PEEK_REG                               (ARM_PERIIOBASE + 0x215094)       // SPI 1 Peek
 245 #define AUX_SPI1_CNTL0_REG                              (ARM_PERIIOBASE + 0x2150C0)       // SPI 2 Control register 0
 246 #define AUX_SPI1_CNTL1_REG                              (ARM_PERIIOBASE + 0x2150C4)       // SPI 2 Control register 1
 247 #define AUX_SPI1_STAT_REG                               (ARM_PERIIOBASE + 0x2150C8)       // SPI 2 Status
 248 #define AUX_SPI1_IO_REG                                 (ARM_PERIIOBASE + 0x2150D0)       // SPI 2 Data
 249 #define AUX_SPI1_PEEK_REG                               (ARM_PERIIOBASE + 0x2150D4)       // SPI 2 Peek
 250
 251 /*
 252     BCM2836
 253  */
 254
 255 #define BCM2836_CTRL                                    (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x000)
 256 #define BCM2836_PRESCALER                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x008)
 257 #define BCM2836_GPU_INT_ROUTING                         (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x00C)
 258 #define BCM2836_PM_ROUTING_SET                          (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x010)
 259 #define BCM2836_PM_ROUTING_CLR                          (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x014)
 260 #define BCM2836_TIMER_LS                                (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x01C)
 261 #define BCM2836_TIMER_MS                                (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x020)
 262 #define BCM2836_INT_ROUTING                             (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x024)
 263 #define BCM2836_AXI_COUNT                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x02C)
 264 #define BCM2836_AXI_IRQ                                 (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x030)
 265 #define BCM2836_TIMER_CTRL                              (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x034)
 266 #define BCM2836_TIMER_WRITE                             (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x038)
 267
 268 #define BCM2836_TIMER_INT_CTRL0                         (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x040)
 269 #define BCM2836_TIMER_INT_CTRL1                         (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x044)
 270 #define BCM2836_TIMER_INT_CTRL2                         (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x048)
 271 #define BCM2836_TIMER_INT_CTRL3                         (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x04C)
 272
 273 #define BCM2836_MAILBOX_INT_CTRL0                       (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x050)
 274 #define BCM2836_MAILBOX_INT_CTRL1                       (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x054)
 275 #define BCM2836_MAILBOX_INT_CTRL2                       (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x058)
 276 #define BCM2836_MAILBOX_INT_CTRL3                       (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x05C)
 277
 278 #define BCM2836_IRQ_PEND0                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x060)
 279 #define BCM2836_IRQ_PEND1                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x064)
 280 #define BCM2836_IRQ_PEND2                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x068)
 281 #define BCM2836_IRQ_PEND3                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x06C)
 282
 283 #define BCM2836_FIQ_PEND0                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x070)
 284 #define BCM2836_FIQ_PEND1                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x074)
 285 #define BCM2836_FIQ_PEND2                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x078)
 286 #define BCM2836_FIQ_PEND3                               (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x07C)
 287
 288 #define BCM2836_MAILBOX0_SET0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x080)
 289 #define BCM2836_MAILBOX1_SET0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x084)
 290 #define BCM2836_MAILBOX2_SET0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x088)
 291 #define BCM2836_MAILBOX3_SET0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x08C)
 292
 293 #define BCM2836_MAILBOX0_SET1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x090)
 294 #define BCM2836_MAILBOX1_SET1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x094)
 295 #define BCM2836_MAILBOX2_SET1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x098)
 296 #define BCM2836_MAILBOX3_SET1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x09C)
 297
 298 #define BCM2836_MAILBOX0_SET2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0A0)
 299 #define BCM2836_MAILBOX1_SET2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0A4)
 300 #define BCM2836_MAILBOX2_SET2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0A8)
 301 #define BCM2836_MAILBOX3_SET2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0AC)
 302
 303 #define BCM2836_MAILBOX0_SET3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0B0)
 304 #define BCM2836_MAILBOX1_SET3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0B4)
 305 #define BCM2836_MAILBOX2_SET3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0B8)
 306 #define BCM2836_MAILBOX3_SET3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0BC)
 307
 308 #define BCM2836_MAILBOX0_CLR0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0C0)
 309 #define BCM2836_MAILBOX1_CLR0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0C4)
 310 #define BCM2836_MAILBOX2_CLR0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0C8)
 311 #define BCM2836_MAILBOX3_CLR0                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0CC)
 312
 313 #define BCM2836_MAILBOX0_CLR1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0D0)
 314 #define BCM2836_MAILBOX1_CLR1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0D4)
 315 #define BCM2836_MAILBOX2_CLR1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0D8)
 316 #define BCM2836_MAILBOX3_CLR1                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0DC)
 317
 318 #define BCM2836_MAILBOX0_CLR2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0E0)
 319 #define BCM2836_MAILBOX1_CLR2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0E4)
 320 #define BCM2836_MAILBOX2_CLR2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0E8)
 321 #define BCM2836_MAILBOX3_CLR2                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0EC)
 322
 323 #define BCM2836_MAILBOX0_CLR3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0F0)
 324 #define BCM2836_MAILBOX1_CLR3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0F4)
 325 #define BCM2836_MAILBOX2_CLR3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0F8)
 326 #define BCM2836_MAILBOX3_CLR3                           (BCM2836_PERIPHYSBASE + BCM2708_PERIPHYSSIZE + 0x0FC)
 327
 328 #endif /* BCM2708_H */