arch/arm-raspi/include/hardware/sdhc.h

   1 /*
   2     Copyright © 2013, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #ifndef _SDHC_H
   7 #define _SDHC_H
   8
   9 #define SDHCI_MAKE_BLCKSIZE(bnd, size)  (((bnd & 0x7) << 12) | (size & 0xFFF))
  10 #define SDHCI_MAKE_CMD(cmd, flags)      (((cmd) << 8) | (flags & 0xFF))
  11 #define SDHCI_GET_CMD(x)                ((x >> 8) & 0x3F)
  12
  13 #define SDHCI_TIMEOUT_MAX               0xE
  14
  15 /* SDHC Registers and Attributes */
  16
  17 #define SDHCI_DMA_ADDRESS               0x00
  18 #define SDHCI_BLOCK_SIZE                0x04
  19 #define SDHCI_BLOCK_COUNT               0x06
  20 #define SDHCI_ARGUMENT                  0x08
  21 #define SDHCI_TRANSFER_MODE             0x0C
  22 #define SDHCI_TRANSMOD_DMA              (1 << 0)
  23 #define SDHCI_TRANSMOD_BLK_CNT_EN       (1 << 1)
  24 #define SDHCI_TRANSMOD_ACMD12           (1 << 2)
  25 #define SDHCI_TRANSMOD_READ             (1 << 4)
  26 #define SDHCI_TRANSMOD_MULTI            (1 << 5)
  27 #define SDHCI_COMMAND                   0x0E
  28 #define SDHCI_CMD_RESP_NONE             (0)
  29 #define SDHCI_CMD_RESP_LONG             (1 << 0)
  30 #define SDHCI_CMD_RESP_SHORT            (1 << 1)
  31 #define SDHCI_CMD_RESP_SHORT_BUSY       (SDHCI_CMD_RESP_LONG|SDHCI_CMD_RESP_SHORT)
  32 #define SDHCI_CMD_RESP_MASK             (SDHCI_CMD_RESP_SHORT_BUSY)
  33 #define SDHCI_CMD_CRC                   (1 << 3)
  34 #define SDHCI_CMD_INDEX                 (1 << 4)
  35 #define SDHCI_CMD_DATA                  (1 << 5)
  36 #define SDHCI_CMD_ABORTCMD              (3 << 6)
  37 #define SDHCI_RESPONSE                  0x10
  38 #define SDHCI_BUFFER                    0x20
  39 #define SDHCI_PRESENT_STATE             0x24
  40 #define SDHCI_PS_CMD_INHIBIT            (1 << 0)
  41 #define SDHCI_PS_DATA_INHIBIT           (1 << 1)
  42 #define SDHCI_PS_DOING_WRITE            (1 << 8)
  43 #define SDHCI_PS_DOING_READ             (1 << 9)
  44 #define SDHCI_PS_SPACE_AVAILABLE        (1 << 10)
  45 #define SDHCI_PS_DATA_AVAILABLE         (1 << 11)
  46 #define SDHCI_PS_CARD_PRESENT           (1 << 16)
  47 #define SDHCI_PS_CARD_STATE_STABLE      (1 << 17)
  48 #define SDHCI_PS_CARD_DETECT_PIN_LVL    (1 << 18)
  49 #define SDHCI_PS_WRITE_PROTECT          (1 << 19)
  50 #define SDHCI_HOST_CONTROL              0x28
  51 #define SDHCI_HCTRL_LED                 (1 << 0)
  52 #define SDHCI_HCTRL_4BITBUS             (1 << 1)
  53 #define SDHCI_HCTRL_HISPD               (1 << 2)
  54 #define SDHCI_HCTRL_DMA_MASK            (3 << 3)
  55 #define SDHCI_HCTRL_SDMA                (0 << 3)
  56 #define SDHCI_HCTRL_ADMA1               (1 << 3)
  57 #define SDHCI_HCTRL_ADMA32              (1 << 4)
  58 #define SDHCI_HCTRL_ADMA64              (SDHCI_HCTRL_ADMA1|SDHCI_HCTRL_ADMA32)
  59 #define SDHCI_HCTRL_8BITBUS             (1 << 5)
  60 #define SDHCI_HCTRL_CD_TEST_INS         (1 << 6)
  61 #define SDHCI_HCTRL_CD_TEST             (1 << 7)
  62 #define SDHCI_POWER_CONTROL             0x29
  63 #define SDHCI_POWER_ON                  (1 << 0)
  64 #define SDHCI_POWER_180                 (1 << 3) | (1 << 1)
  65 #define SDHCI_POWER_300                 (1 << 3) | (1 << 2)
  66 #define SDHCI_POWER_330                 (1 << 3) | (1 << 2) | (1 << 1)
  67 #define SDHCI_BLOCK_GAP_CONTROL         0x2A
  68 #define SDHCI_WAKE_UP_CONTROL           0x2B
  69 #define SDHCI_WAKE_ONINT                (1 << 0)
  70 #define SDHCI_WAKE_ONINSERT             (1 << 1)
  71 #define SDHCI_WAKE_ONREMOVE             (1 << 2)
  72 #define SDHCI_CLOCK_CONTROL             0x2C
  73 #define SDHCI_CLOCK_INT_EN              (1 << 0)
  74 #define SDHCI_CLOCK_INT_STABLE          (1 << 1)
  75 #define SDHCI_CLOCK_CARD_EN             (1 << 2)
  76 #define SDHCI_DIVIDER_SHIFT             (8)
  77 #define SDHCI_DIVIDER_HI_SHIFT          (6)
  78 #define SDHCI_DIV_MASK                  (0xFF)
  79 #define SDHCI_DIV_MASK_LEN              (8)
  80 #define SDHCI_DIV_HI_MASK               (3 << 8)
  81 #define SDHCI_TIMEOUT_CONTROL           0x2E
  82 #define SDHCI_RESET                     0x2F
  83 #define SDHCI_RESET_ALL                 (1 << 0)
  84 #define SDHCI_RESET_CMD                 (1 << 1)
  85 #define SDHCI_RESET_DATA                (1 << 2)
  86 #define SDHCI_INT_STATUS                0x30
  87 #define SDHCI_INT_ENABLE                0x34
  88 #define SDHCI_SIGNAL_ENABLE             0x38
  89 #define SDHCI_INT_RESPONSE              (1 << 0)
  90 #define SDHCI_INT_DATA_END              (1 << 2)
  91 #define SDHCI_INT_DMA_END               (1 << 3)
  92 #define SDHCI_INT_SPACE_AVAIL           (1 << 4)
  93 #define SDHCI_INT_DATA_AVAIL            (1 << 5)
  94 #define SDHCI_INT_CARD_INSERT           (1 << 6)
  95 #define SDHCI_INT_CARD_REMOVE           (1 << 7)
  96 #define SDHCI_INT_CARD_INT              (1 << 8)
  97 #define SDHCI_INT_ERROR                 (1 << 15)
  98 #define SDHCI_INT_TIMEOUT               (1 << 16)
  99 #define SDHCI_INT_CRC                   (1 << 17)
 100 #define SDHCI_INT_END_BIT               (1 << 18)
 101 #define SDHCI_INT_INDEX                 (1 << 19)
 102 #define SDHCI_INT_DATA_TIMEOUT          (1 << 20)
 103 #define SDHCI_INT_DATA_CRC              (1 << 21)
 104 #define SDHCI_INT_DATA_END_BIT          (1 << 22)
 105 #define SDHCI_INT_BUS_POWER             (1 << 23)
 106 #define SDHCI_INT_ACMD12ERR             (1 << 24)
 107 #define SDHCI_INT_ADMA_ERROR            (1 << 25)
 108 #define SDHCI_INT_CMD_MASK              (SDHCI_INT_RESPONSE|SDHCI_INT_TIMEOUT|SDHCI_INT_CRC|SDHCI_INT_END_BIT|SDHCI_INT_INDEX)
 109 #define SDHCI_INT_DATA_MASK             (SDHCI_INT_DATA_END|SDHCI_INT_DMA_END|SDHCI_INT_DATA_AVAIL|SDHCI_INT_SPACE_AVAIL|SDHCI_INT_DATA_TIMEOUT|SDHCI_INT_DATA_CRC|SDHCI_INT_DATA_END_BIT|SDHCI_INT_ADMA_ERROR)
 110 #define SDHCI_INT_ALL_MASK              (0xFFFFFFFF)
 111 #define SDHCI_INT_NORMAL_MASK           (0x00007FFF)
 112 #define SDHCI_INT_ERROR_MASK            (0xFFFF8000)
 113 #define SDHCI_ACMD12_ERR                0x3C
 114 #define SDHCI_CAPABILITIES              0x40
 115 #define SDHCI_TIMEOUT_CLK_MASK          (0x3F)
 116 #define SDHCI_TIMEOUT_CLK_SHIFT         (0)
 117 #define SDHCI_TIMEOUT_CLK_UNIT          (1 << 7)
 118 #define SDHCI_CLOCK_BASE_SHIFT          (8)
 119 #define SDHCI_CLOCK_BASE_MASK           (0x3F << SDHCI_CLOCK_BASE_SHIFT)
 120 #define SDHCI_CLOCK_V3_BASE_MASK        (0xFF << SDHCI_CLOCK_BASE_SHIFT)
 121 #define SDHCI_MAX_BLOCK_SHIFT           (16)
 122 #define SDHCI_MAX_BLOCK_MASK            (0x03 << SDHCI_MAX_BLOCK_SHIFT)
 123 #define SDHCI_CAN_DO_8BIT               (1 << 18)
 124 #define SDHCI_CAN_DO_ADMA2              (1 << 19)
 125 #define SDHCI_CAN_DO_ADMA1              (1 << 20)
 126 #define SDHCI_CAN_DO_HISPD              (1 << 21)
 127 #define SDHCI_CAN_DO_SDMA               (1 << 22)
 128 #define SDHCI_CAN_VDD_330               (1 << 24)
 129 #define SDHCI_CAN_VDD_300               (1 << 25)
 130 #define SDHCI_CAN_VDD_180               (1 << 26)
 131 #define SDHCI_CAN_64BIT                 (1 << 27)
 132 #define SDHCI_CAPABILITIES1             0x44
 133 #define SDHCI_MAX_CURRENT               0x48
 134 #define SDHCI_SET_ACMD12_ERROR          0x50
 135 #define SDHCI_SET_INT_ERROR             0x52
 136 #define SDHCI_ADMA_ERROR                0x54
 137 #define SDHCI_ADMA_ADDRESS              0x58
 138 #define SDHCI_SLOT_INT_STATUS           0xFC
 139 #define SDHCI_HOST_VERSION              0xFE
 140 #define SDHCI_HVERS_SPEC_SHIFT          (0)
 141 #define SDHCI_HVERS_SPEC_MASK           (0xFF)
 142 #define SDHCI_HVERS_VENDVER_SHIFT       (8)
 143 #define SDHCI_HVERS_VENDVER_MASK        (SDHCI_HVERS_SPEC_MASK << SDHCI_HVERS_VENDVER_SHIFT)
 144 #define SDHCI_HVERS_SPEC100             (0)
 145 #define SDHCI_HVERS_SPEC200             (1 << 0)
 146 #define SDHCI_HVERS_SPEC300             (1 << 2)
 147
 148 /* SDCard OCR Values */
 149 #define OCR_S18R                        (1 << 24) // 1.8v switching
 150 #define OCR_XPC                         (1 << 28) // SDXC power control
 151 #define OCR_FASTBOOT                    (1 << 29)
 152 #define OCR_HCS                         (1 << 30) // High-Capacity support
 153 #define OCR_BUSY                        (1 << 31)
 154
 155 #define SD_SCR_HIGHSPEED                (1 << 17)
 156 #define SD_SCR_DATA4BIT                 (1 << 18)
 157
 158 /* SDCard Commands */
 159 #define SD_CMD_SEND_RELATIVE_ADDR       3
 160 #define SD_CMD_SWITCH_FUNC              6
 161 #define SD_CMD_SEND_IF_COND             8
 162
 163 #define SD_CMD_APP_SET_BUS_WIDTH        6
 164 #define SD_CMD_ERASE_WR_BLK_START       32
 165 #define SD_CMD_ERASE_WR_BLK_END         33
 166 #define SD_CMD_APP_SEND_OP_COND         41
 167 #define SD_CMD_APP_SEND_SCR             51
 168
 169 #endif /* _SDHC_H */