rom/usb/pciusb/xhcichip.h

   1 #ifndef XHCICHIP_H
   2 #define XHCICHIP_H
   3
   4 /*
   5  *----------------------------------------------------------------------------
   6  *             Includes for XHCI USB Controller
   7  *----------------------------------------------------------------------------
   8  */
   9
  10 /*
  11     XHCI_xxx's are offsets to something
  12     XHCB_xxx's are bitnumbers
  13     XHCF_xxx's are flags
  14     XHCM_xxx's are bitmasks
  15     XHCV_xxx(p)'s return shifted values from p
  16 */
  17
  18 #define opreg_readl(opreg) READREG32_LE(hc->xhc_opregbase, opreg)
  19 #define opreg_writel(opreg, value) WRITEREG32_LE(hc->xhc_opregbase, opreg, value)
  20 #define opreg_writeq(opreg, value) WRITEREG64_LE(hc->xhc_opregbase, opreg, value)
  21
  22 #define capreg_readl(capreg) READREG32_LE(hc->xhc_capregbase, capreg)
  23 #define capreg_readw(capreg) READREG16_LE(hc->xhc_capregbase, capreg)
  24 #define capreg_readb(capreg) (*((volatile UBYTE *) (((UBYTE *) (hc->xhc_capregbase)) + ((ULONG) (capreg)))))
  25
  26
  27 /* XHCI capability register defines */
  28 #define XHCI_CAPLENGTH  0x00
  29 #define XHCI_HCIVERSION 0x02
  30 #define XHCI_HCSPARAMS1 0x04
  31 #define XHCI_HCSPARAMS2 0x08
  32 #define XHCI_HCSPARAMS3 0x0C
  33 #define XHCI_HCCPARAMS  0x10
  34 #define XHCI_DBOFF      0x14
  35 #define XHCI_RTSOFF     0x18
  36
  37
  38 /* XHCI_HCSPARAMS1 defines */
  39 #define XHCB_MaxSlots   0
  40 #define XHCB_MaxIntrs   8
  41 #define XHCB_MaxPorts   24
  42
  43 #define XHCM_MaxSlots (((1UL<<8)-1)<<XHCB_MaxSlots)
  44 #define XHCM_MaxIntrs (((1UL<<11)-1)<<XHCB_MaxIntrs)
  45 #define XHCM_MaxPorts (((1UL<<8)-1)<<XHCB_MaxPorts)
  46
  47 #define XHCV_MaxPorts(p)    (((p)&XHCM_MaxPorts)>>XHCB_MaxPorts)
  48 #define XHCV_MaxIntrs(p)    (((p)&XHCM_MaxIntrs)>>XHCB_MaxIntrs)
  49 #define XHCV_MaxSlots(p)    (((p)&XHCM_MaxSlots)>>XHCB_MaxSlots)
  50
  51
  52 /* XHCI_HCSPARAMS2 defines */
  53 #define XHCB_IST        0
  54 #define XHCB_ERST_Max   4
  55 #define XHCB_SPR        26
  56 #define XHCB_SPB_Max    27
  57
  58 #define XHCM_IST        (((1UL<<4)-1)<<XHCB_IST)
  59 #define XHCM_ERST_Max   ((1UL<<4)-1)<<XHCB_ERST_Max)
  60 #define XHCF_SPR        (1UL<<XHCB_SPR)
  61 #define XHCM_SPB_Max    (((1UL<<5)-1)<<XHCB_SPB_Max)
  62 #define XHCV_SPB_Max(p) (((p)&XHCM_SPB_Max)>>XHCB_SPB_Max)
  63
  64 #define XHCI_MAX_SCRATCHPADS    31
  65
  66 /* XHCI_HCSPARAMS3 defines */
  67 #define XHCB_U1DEV_LAT  0
  68 #define XHCB_U2DEV_LAT  16
  69
  70 #define XHCM_U1DEV_LAT  (((1UL<<8)-1)<<XHCB_U1DEV_LAT)
  71 #define XHCM_U2DEV_LAT  (((1UL<<16)-1)<<XHCB_U2DEV_LAT)
  72
  73
  74 /* XHCI_HCCPARAMS defines */
  75 #define XHCB_AC64       0
  76 #define XHCB_BNC        1
  77 #define XHCB_CSZ        2
  78 #define XHCB_PPC        3
  79 #define XHCB_PIND       4
  80 #define XHCB_LHRC       5
  81 #define XHCB_LTC        6
  82 #define XHCB_NSS        7
  83 #define XHCB_MaxPSASize 12
  84 #define XHCB_xECP       16
  85
  86 #define XHCF_AC64       (1UL<<XHCB_AC64)
  87 #define XHCF_BNC        (1UL<<XHCB_BNC)
  88 #define XHCF_CSZ        (1UL<<XHCB_CSZ)
  89 #define XHCF_PPC        (1UL<<XHCB_PPC)
  90 #define XHCF_PIND       (1UL<<XHCB_PIND)
  91 #define XHCF_LHRC       (1UL<<XHCB_LHRC)
  92 #define XHCF_LTC        (1UL<<XHCB_LTC)
  93 #define XHCF_NSS        (1UL<<XHCB_NSS)
  94 #define XHCM_MaxPSASize (((1UL<<4)-1)<<XHCB_MaxPSASize)
  95 #define XHCM_xECP       (((1UL<<16)-1)<<XHCB_xECP)
  96 #define XHCV_xECP(p)    ((((p)&XHCM_xECP)>>XHCB_xECP)<<2)
  97
  98
  99 /* Extended capability IDs */
 100 #define XHCB_EXT_CAPS_ID        0
 101 #define XHCB_EXT_CAPS_NEXT      8
 102 #define XHCB_EXT_CAPS_VALUE     16
 103
 104 #define XHCM_EXT_CAPS_ID        (((1UL<<8)-1)<<XHCB_EXT_CAPS_ID)
 105 #define XHCM_EXT_CAPS_NEXT      (((1UL<<8)-1)<<XHCB_EXT_CAPS_NEXT)
 106 #define XHCM_EXT_CAPS_VALUE     (((1UL<<16)-1)<<XHCB_EXT_CAPS_VALUE)
 107
 108 #define XHCV_EXT_CAPS_ID(p)     (((p)&XHCM_EXT_CAPS_ID)>>XHCB_EXT_CAPS_ID)
 109 #define XHCV_EXT_CAPS_NEXT(p)   ((((p)&XHCM_EXT_CAPS_NEXT)>>XHCB_EXT_CAPS_NEXT)<<2)
 110 #define XHCV_EXT_CAPS_VALUE(p)  (((p)&XHCM_EXT_CAPS_VALUE)>>XHCB_EXT_CAPS_VALUE)
 111
 112
 113 /* Reserved ID 0 */
 114 #define XHCI_EXT_CAPS_LEGACY    1
 115 #define XHCI_EXT_CAPS_PROTOCOL  2
 116 #define XHCI_EXT_CAPS_XPOWERMNG 3
 117 #define XHCI_EXT_CAPS_IOVIRT    4
 118 #define XHCI_EXT_CAPS_MSGINTR   5
 119 #define XHCI_EXT_CAPS_LOCALMEM  6
 120 /* Reserved IDs 7-9 */
 121 #define XHCI_EXT_CAPS_USBDEBUG  10
 122 /* Reserved IDs 11-16 */
 123 #define XHCI_EXT_CAPS_XMSGINTR  17
 124 /* Reserved IDs 18-191 */
 125 /* Vendor defined IDs 192-255 */
 126 #define XHCI_EXT_CAPS_MAX       255
 127
 128
 129 /* These are for XHCI_EXT_CAPS_LEGACY */
 130 /* USB Legacy Support Capability (USBLEGSUP) */
 131 #define XHCI_USBLEGSUP   0x00
 132 #define XHCB_BIOSOWNED   16
 133 #define XHCB_OSOWNED     24
 134 #define XHCF_BIOSOWNED  (1UL<<XHCB_BIOSOWNED)
 135 #define XHCF_OSOWNED    (1UL<<XHCB_OSOWNED)
 136
 137 /* USB Legacy Support Control/Status (USBLEGCTLSTS) */
 138 #define XHCI_USBLEGCTLSTS       0x04
 139 #define XHCB_SMI_USBE           0
 140 #define XHCB_SMI_HSEE           4
 141 #define XHCB_SMI_OSOE           13
 142 #define XHCB_SMI_PCICE          14
 143 #define XHCB_SMI_BARE           15
 144 #define XHCB_SMI_EI             16
 145 #define XHCB_SMI_HSE            20
 146 #define XHCB_SMI_OSOC           29
 147 #define XHCB_SMI_PCIC           30
 148 #define XHCB_SMI_BAR            31
 149
 150 #define XHCF_SMI_USBE           (1UL<<XHCB_SMI_USBE)
 151 #define XHCF_SMI_HSEE           (1UL<<XHCB_SMI_HSEE)
 152 #define XHCF_SMI_OSOE           (1UL<<XHCB_SMI_OSOE)
 153 #define XHCF_SMI_PCICE          (1UL<<XHCB_SMI_PCICE)
 154 #define XHCF_SMI_BARE           (1UL<<XHCB_SMI_BARE)
 155 #define XHCF_SMI_EI             (1UL<<XHCB_SMI_EI)
 156 #define XHCF_SMI_HSE            (1UL<<XHCB_SMI_HSE)
 157 #define XHCF_SMI_OSOC           (1UL<<XHCB_SMI_OSOC)
 158 #define XHCF_SMI_PCIC           (1UL<<XHCB_SMI_PCIC)
 159 #define XHCF_SMI_BAR            (1UL<<XHCB_SMI_BAR)
 160
 161
 162 /* These are for XHCI_EXT_CAPS_PROTOCOL */
 163 /* xHCI Supported Protocol Capability Field Definitions */
 164 #define XHCI_SPFD               0x00
 165 #define XHCB_SPFD_RMINOR        16
 166 #define XHCB_SPFD_RMAJOR        24
 167
 168 #define XHCM_SPFD_RMINOR        (((1UL<<8)-1)<<XHCB_SPFD_RMINOR)
 169 #define XHCM_SPFD_RMAJOR        (((1UL<<8)-1)<<XHCB_SPFD_RMAJOR)
 170
 171 #define XHCV_SPFD_RMINOR(p)    (((p)&XHCM_SPFD_RMINOR)>>XHCB_SPFD_RMINOR)
 172 #define XHCV_SPFD_RMAJOR(p)    (((p)&XHCM_SPFD_RMAJOR)>>XHCB_SPFD_RMAJOR)
 173
 174 #define XHCI_SPNAMESTRING       0x04
 175
 176 #define XHCI_SPPORT             0x08
 177 #define XHCB_SPPORT_CPO         0       /* Compatible Port Offset */
 178 #define XHCB_SPPORT_CPCNT       8       /* Compatible Port Count */
 179 #define XHCB_SPPORT_PD          16      /* Protocol Defined */
 180 #define XHCB_SPPORT_PSIC        28      /* Protocol Speed ID Count */
 181
 182 #define XHCM_SPPORT_CPO         (((1UL<<8)-1)<<XHCB_SPPORT_CPO)
 183 #define XHCM_SPPORT_CPCNT       (((1UL<<8)-1)<<XHCB_SPPORT_CPCNT)
 184 #define XHCM_SPPORT_PD          (((1UL<<12)-1)<<XHCB_SPPORT_PD)
 185 #define XHCM_SPPORT_PSIC        (((1UL<<4)-1)<<XHCB_SPPORT_PSIC)
 186
 187 #define XHCV_SPPORT_CPO(p)      (((p)&XHCM_SPPORT_CPO)>>XHCB_SPPORT_CPO)
 188 #define XHCV_SPPORT_CPCNT(p)    (((p)&XHCM_SPPORT_CPCNT)>>XHCB_SPPORT_CPCNT)
 189 #define XHCV_SPPORT_PD(p)       (((p)&XHCM_SPPORT_PD)>>XHCB_SPPORT_PD)
 190 #define XHCV_SPPORT_PSIC(p)     (((p)&XHCM_SPPORT_PSIC)>>XHCB_SPPORT_PSIC)
 191
 192 #define XHCI_SPPSI(psic) ((psic *4) + 0x10 )
 193 /* XHCI operational register defines */
 194 /* USB Command Register (USBCMD) */
 195 #define XHCI_USBCMD     0x00
 196
 197 #define XHCB_CMD_RS     0
 198 #define XHCB_CMD_HCRST  1
 199 #define XHCB_CMD_INTE   2
 200 #define XHCB_CMD_HSEE   3
 201 #define XHCB_CMD_LHCRST 7
 202 #define XHCB_CMD_CSS    8
 203 #define XHCB_CMD_CRS    9
 204 #define XHCB_CMD_EWE    10
 205 #define XHCB_CMD_EU3S   11
 206
 207 #define XHCF_CMD_RS     (1UL<<XHCB_CMD_RS)
 208 #define XHCF_CMD_HCRST  (1UL<<XHCB_CMD_HCRST)
 209 #define XHCF_CMD_INTE   (1UL<<XHCB_CMD_INTE)
 210 #define XHCF_CMD_HSEE   (1UL<<XHCB_CMD_HSEE)
 211 #define XHCF_CMD_LHCRST (1UL<<XHCB_CMD_LHCRST)
 212 #define XHCF_CMD_CSS    (1UL<<XHCB_CMD_CSS)
 213 #define XHCF_CMD_CRS    (1UL<<XHCB_CMD_CRS)
 214 #define XHCF_CMD_EWE    (1UL<<XHCB_CMD_EWE)
 215 #define XHCF_CMD_EU3S   (1UL<<XHCB_CMD_EU3S)
 216
 217 /* USB Status Register (USBSTS) */
 218 #define XHCI_USBSTS     0x04
 219 #define XHCB_STS_HCH    0
 220 #define XHCB_STS_HSE    2
 221 #define XHCB_STS_EINT   3
 222 #define XHCB_STS_PCD    4
 223 #define XHCB_STS_SSS    8
 224 #define XHCB_STS_RSS    9
 225 #define XHCB_STS_SRE    10
 226 #define XHCB_STS_CNR    11
 227 #define XHCB_STS_HCE    12
 228
 229 #define XHCF_STS_HCH    (1UL<<XHCB_STS_HCH)
 230 #define XHCF_STS_HSE    (1UL<<XHCB_STS_HSE)
 231 #define XHCF_STS_EINT   (1UL<<XHCB_STS_EINT)
 232 #define XHCF_STS_PCD    (1UL<<XHCB_STS_PCD)
 233 #define XHCF_STS_SSS    (1UL<<XHCB_STS_SSS)
 234 #define XHCF_STS_RSS    (1UL<<XHCB_STS_RSS)
 235 #define XHCF_STS_SRE    (1UL<<XHCB_STS_SRE)
 236 #define XHCF_STS_CNR    (1UL<<XHCB_STS_CNR)
 237 #define XHCF_STS_HCE    (1UL<<XHCB_STS_HCE)
 238
 239 /* Page Size Register (PAGESIZE) */
 240 #define XHCI_PAGESIZE   0x08
 241
 242 /* Device Notification Control Register (DNCTRL) */
 243 #define XHCI_DNCTRL     0x14
 244
 245 /* Command Ring Control Register (CRCR) */
 246 #define XHCI_CRCR       0x18
 247
 248 /* Device Context Base Address Array Pointer Register (DCBAAP) */
 249 #define XHCI_DCBAAP     0x30
 250
 251 /* Configure Register (CONFIG) */
 252 #define XHCI_CONFIG     0x38
 253 #define XHCB_CONFIG_MaxSlotsEn  0
 254 #define XHCM_CONFIG_MaxSlotsEn  (((1UL<<8)-1)<<XHCB_CONFIG_MaxSlotsEn)
 255
 256 /* Port Status and Control Register (PORTSC) */
 257 #define XHCI_PORTSC(port) (0x400 + (0x10 * (port-1)))
 258
 259 #define XHCB_PS_CCS     0
 260 #define XHCB_PS_PED     1
 261 #define XHCB_PS_OCA     3
 262 #define XHCB_PS_PR      4
 263 #define XHCB_PS_PLS     5
 264 #define XHCB_PS_PP      9
 265 #define XHCB_PS_SPEED   10
 266 #define XHCB_PS_PIC     14
 267 #define XHCB_PS_LWS     16
 268 #define XHCB_PS_CSC     17
 269 #define XHCB_PS_PEC     18
 270 #define XHCB_PS_WRC     19
 271 #define XHCB_PS_OCC     20
 272 #define XHCB_PS_PRC     21
 273 #define XHCB_PS_PLC     22
 274 #define XHCB_PS_CEC     23
 275 #define XHCB_PS_CAS     24
 276 #define XHCB_PS_WCE     25
 277 #define XHCB_PS_WDE     26
 278 #define XHCB_PS_WOE     27
 279 #define XHCB_PS_DR      30
 280 #define XHCB_PS_WPR     31
 281
 282 #define XHCF_PS_CCS     (1UL<<XHCB_PS_CCS)
 283 #define XHCF_PS_PED     (1UL<<XHCB_PS_PED)
 284 #define XHCF_PS_OCA     (1UL<<XHCB_PS_OCA)
 285 #define XHCF_PS_PR      (1UL<<XHCB_PS_PR)
 286 #define XHCM_PS_PLS     (((1UL<<4)-1)<<XHCB_PS_PLS)
 287 #define XHCF_PS_PP      (1UL<<XHCB_PS_PP)
 288 #define XHCM_PS_SPEED   (((1UL<<4)-1)<<XHCB_PS_SPEED)
 289 #define XHCM_PS_PIC     (((1UL<<2)-1)<<XHCB_PS_PIC)
 290 #define XHCF_PS_LWS     (1UL<<XHCB_PS_LWS)
 291 #define XHCF_PS_CSC     (1UL<<XHCB_PS_CSC)
 292 #define XHCF_PS_PEC     (1UL<<XHCB_PS_PEC)
 293 #define XHCF_PS_WRC     (1UL<<XHCB_PS_WRC)
 294 #define XHCF_PS_OCC     (1UL<<XHCB_PS_OCC)
 295 #define XHCF_PS_PRC     (1UL<<XHCB_PS_PRC)
 296 #define XHCF_PS_PLC     (1UL<<XHCB_PS_PLC)
 297 #define XHCF_PS_CEC     (1UL<<XHCB_PS_CEC)
 298 #define XHCF_PS_CAS     (1UL<<XHCB_PS_CAS)
 299 #define XHCF_PS_WCE     (1UL<<XHCB_PS_WCE)
 300 #define XHCF_PS_WDE     (1UL<<XHCB_PS_WDE)
 301 #define XHCF_PS_WOE     (1UL<<XHCB_PS_WOE)
 302 #define XHCF_PS_DR      (1UL<<XHCB_PS_DR)
 303 #define XHCF_PS_WPR     (1UL<<XHCB_PS_WPR)
 304 #define XHCV_PS_SPEED(p)    (((p)&XHCM_PS_SPEED)>>XHCB_PS_SPEED)
 305
 306 #endif /* XHCICHIP_H */