rom/usb/pciusb/pciusb.h

   1 #ifndef PCIUSB_H
   2 #define PCIUSB_H
   3
   4 /*
   5  *----------------------------------------------------------------------------
   6  *                         Includes for pciusb.device
   7  *----------------------------------------------------------------------------
   8  *                   By Chris Hodges <chrisly@platon42.de>
   9  */
  10
  11 #include LC_LIBDEFS_FILE
  12
  13 #include <aros/libcall.h>
  14 #include <aros/asmcall.h>
  15 #include <aros/symbolsets.h>
  16
  17 #include <exec/types.h>
  18 #include <exec/lists.h>
  19 #include <exec/memory.h>
  20 #include <exec/libraries.h>
  21 #include <exec/interrupts.h>
  22 #include <exec/semaphores.h>
  23 #include <exec/execbase.h>
  24 #include <exec/devices.h>
  25 #include <exec/io.h>
  26 #include <exec/ports.h>
  27 #include <exec/errors.h>
  28 #include <exec/resident.h>
  29 #include <exec/initializers.h>
  30 #include <dos/dos.h>
  31
  32 #include <devices/timer.h>
  33 #include <utility/utility.h>
  34
  35 #include <devices/usbhardware.h>
  36 #include <devices/newstyle.h>
  37
  38 #include <oop/oop.h>
  39 #include <hidd/irq.h>
  40
  41 #include "debug.h"
  42
  43 /* Reply the iorequest with success */
  44 #define RC_OK         0
  45
  46 /* Magic cookie, don't set error fields & don't reply the ioreq */
  47 #define RC_DONTREPLY  -1
  48
  49 #define MAX_ROOT_PORTS   16
  50 #define MAX_USB3_PORTS   255
  51
  52 #define PCI_CLASS_SERIAL_USB 0x0c03
  53
  54 /* The unit node - private */
  55 struct PCIUnit
  56 {
  57     struct Unit           hu_Unit;
  58     LONG                  hu_UnitNo;
  59
  60     struct PCIDevice     *hu_Device;         /* Uplink */
  61
  62     struct MsgPort       *hu_MsgPort;
  63     struct timerequest   *hu_TimerReq;       /* Timer I/O Request */
  64
  65     struct timerequest    hu_LateIOReq;      /* Timer I/O Request */
  66     struct MsgPort        hu_LateMsgPort;
  67
  68     struct timerequest    hu_NakTimeoutReq;
  69     struct MsgPort        hu_NakTimeoutMsgPort;
  70     struct Interrupt      hu_NakTimeoutInt;
  71
  72     BOOL                  hu_UnitAllocated;  /* Unit opened */
  73
  74     ULONG                 hu_DevID;          /* Device ID (BusID+DevNo) */
  75     struct List           hu_Controllers;    /* List of controllers */
  76     UWORD                 hu_RootHub11Ports;
  77     UWORD                 hu_RootHub20Ports;
  78 #ifdef AROS_USB30_CODE
  79     UWORD                 hu_RootHub30Ports;
  80 #endif
  81     UWORD                 hu_RootHubPorts;
  82     UWORD                 hu_RootHubAddr;    /* Root Hub Address */
  83     UWORD                 hu_RootPortChanges; /* Merged root hub changes */
  84     ULONG                 hu_FrameCounter;   /* Common frame counter */
  85     struct List           hu_RHIOQueue;      /* Root Hub Pending IO Requests */
  86
  87     struct PCIController *hu_PortMap11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 controller */
  88     struct PCIController *hu_PortMap20[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 2.0 controller */
  89 #ifdef AROS_USB30_CODE
  90     struct PCIController *hu_PortMap30[MAX_USB3_PORTS]; /* Maps from Global Port to USB 3.0 controller */
  91 #endif
  92     UBYTE                 hu_PortNum11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 companion controller port */
  93     UBYTE                 hu_EhciOwned[MAX_ROOT_PORTS]; /* TRUE, if currently owned by EHCI */
  94     UBYTE                 hu_ProductName[80]; /* for Query device */
  95     struct PCIController *hu_DevControllers[128]; /* maps from Device address to controller */
  96     struct IOUsbHWReq    *hu_DevBusyReq[128*16*2]; /* pointer to io assigned to the Endpoint */
  97     ULONG                 hu_NakTimeoutFrame[128*16*2]; /* Nak Timeout framenumber */
  98     UBYTE                 hu_DevDataToggle[128*16*2]; /* Data toggle bit for endpoints */
  99 };
 100
 101 #define HCITYPE_UHCI     0x00
 102 #define HCITYPE_OHCI     0x10
 103 #define HCITYPE_EHCI     0x20
 104 #ifdef AROS_USB30_CODE
 105 #define HCITYPE_XHCI     0x30
 106 #endif
 107
 108 struct PCIController
 109 {
 110     struct Node           hc_Node;
 111     struct PCIDevice     *hc_Device;        /* Uplink */
 112     struct PCIUnit       *hc_Unit;          /* Uplink */
 113
 114     OOP_Object           *hc_PCIDeviceObject;
 115     OOP_Object           *hc_PCIDriverObject;
 116     ULONG                 hc_DevID;
 117     UWORD                 hc_FunctionNum;
 118     UWORD                 hc_HCIType;
 119     UWORD                 hc_NumPorts;
 120     UWORD                 hc_Flags;         /* See below */
 121
 122     volatile APTR         hc_RegBase;
 123
 124     #ifdef AROS_USB30_CODE
 125     volatile APTR         xhc_capregbase;
 126     volatile APTR         xhc_opregbase;
 127     ULONG                 xhc_pagesize;
 128     ULONG                 xhc_scratchbufs;
 129     ULONG                 xhc_maxslots;
 130     APTR                  xhc_dcbaa;
 131     APTR                  xhc_dcbaa_original;
 132     BOOL                  xhc_contextsize64;
 133
 134     UWORD                 xhc_NumPorts;
 135     UWORD                 xhc_NumPorts20;
 136     UWORD                 xhc_NumPorts30;
 137     #endif
 138
 139     APTR                  hc_PCIMem;
 140     ULONG                 hc_PCIMemSize;
 141     IPTR                  hc_PCIVirtualAdjust;
 142     IPTR                  hc_PCIIntLine;
 143     HIDDT_IRQ_Handler     hc_PCIIntHandler;
 144     ULONG                 hc_PCIIntEnMask;
 145
 146     ULONG                *hc_UhciFrameList;
 147     struct UhciQH        *hc_UhciQHPool;
 148     struct UhciTD        *hc_UhciTDPool;
 149
 150     struct UhciQH        *hc_UhciCtrlQH;
 151     struct UhciQH        *hc_UhciBulkQH;
 152     struct UhciQH        *hc_UhciIntQH[9];
 153     struct UhciTD        *hc_UhciIsoTD;
 154     struct UhciQH        *hc_UhciTermQH;
 155
 156     ULONG                 hc_EhciUsbCmd;
 157     ULONG                *hc_EhciFrameList;
 158     struct EhciQH        *hc_EhciQHPool;
 159     struct EhciTD        *hc_EhciTDPool;
 160
 161     struct EhciQH        *hc_EhciAsyncQH;
 162     struct EhciQH        *hc_EhciIntQH[11];
 163     struct EhciQH        *hc_EhciTermQH;
 164     volatile BOOL         hc_AsyncAdvanced;
 165     struct EhciQH        *hc_EhciAsyncFreeQH;
 166     struct EhciTD        *hc_ShortPktEndTD;
 167
 168     struct OhciED        *hc_OhciCtrlHeadED;
 169     struct OhciED        *hc_OhciCtrlTailED;
 170     struct OhciED        *hc_OhciBulkHeadED;
 171     struct OhciED        *hc_OhciBulkTailED;
 172     struct OhciED        *hc_OhciIntED[5];
 173     struct OhciED        *hc_OhciTermED;
 174     struct OhciTD        *hc_OhciTermTD;
 175     struct OhciHCCA      *hc_OhciHCCA;
 176     struct OhciED        *hc_OhciEDPool;
 177     struct OhciTD        *hc_OhciTDPool;
 178     struct OhciED        *hc_OhciAsyncFreeED;
 179     ULONG                 hc_OhciDoneQueue;
 180     struct List           hc_OhciRetireQueue;
 181
 182     ULONG                 hc_FrameCounter;
 183     struct List           hc_TDQueue;
 184     struct List           hc_AbortQueue;
 185     struct List           hc_PeriodicTDQueue;
 186     struct List           hc_CtrlXFerQueue;
 187     struct List           hc_IntXFerQueue;
 188     struct List           hc_IsoXFerQueue;
 189     struct List           hc_BulkXFerQueue;
 190
 191     struct Interrupt      hc_CompleteInt;
 192     struct Interrupt      hc_ResetInt;
 193
 194     UBYTE                 hc_PortNum20[MAX_ROOT_PORTS];     /* Global Port number the local controller port corresponds with */
 195
 196     UWORD                 hc_PortChangeMap[MAX_ROOT_PORTS]; /* Port Change Map */
 197
 198     BOOL                  hc_complexrouting;
 199     ULONG                 hc_portroute;
 200
 201 };
 202
 203 /* hc_Flags */
 204 #define HCF_ALLOCATED   0x0001  /* PCI board allocated           */
 205 #define HCF_ONLINE      0x0002  /* Online                        */
 206 #define HCF_STOP_BULK   0x0004  /* Bulk transfers stopped        */
 207 #define HCF_STOP_CTRL   0x0008  /* Control transfers stopped     */
 208 #define HCF_ABORT       0x0010  /* Aborted requests available    */
 209
 210 /* The device node - private
 211 */
 212 struct PCIDevice
 213 {
 214     struct Library      hd_Library;       /* standard */
 215     UWORD               hd_Flags;         /* various flags */
 216
 217     struct UtilityBase *hd_UtilityBase;   /* for tags etc */
 218
 219     struct List         hd_TempHCIList;
 220     OOP_Object         *hd_PCIHidd;
 221     OOP_Object         *hd_IRQHidd;
 222     OOP_AttrBase        hd_HiddAB;
 223     OOP_AttrBase        hd_HiddPCIDeviceAB;
 224
 225     BOOL                hd_ScanDone;      /* PCI scan done? */
 226     APTR                hd_MemPool;       /* Memory Pool */
 227
 228         struct List         hd_Units;         /* List of units */
 229 };
 230
 231 /* hd_Flags */
 232 #define HDF_FORCEPOWER  0x01
 233
 234 #endif /* PCIUSB_H */