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revert between 56095 -> 55830 in arch
[AROS.git] / workbench / devs / networks / e1000 / e1000_mac.c
bloba77becd2494a699099813746f610b49cfd8e1876
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include "e1000_api.h"
30
31 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
32 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
33
34 /**
35 * e1000_init_mac_ops_generic - Initialize MAC function pointers
36 * @hw: pointer to the HW structure
37 *
38 * Setups up the function pointers to no-op functions
39 **/
40 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
41 {
42 struct e1000_mac_info *mac = &hw->mac;
43 DEBUGFUNC("e1000_init_mac_ops_generic");
44
45 /* General Setup */
46 mac->ops.init_params = e1000_null_ops_generic;
47 mac->ops.init_hw = e1000_null_ops_generic;
48 mac->ops.reset_hw = e1000_null_ops_generic;
49 mac->ops.setup_physical_interface = e1000_null_ops_generic;
50 mac->ops.get_bus_info = e1000_null_ops_generic;
51 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
52 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
53 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
54 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
55 /* LED */
56 mac->ops.cleanup_led = e1000_null_ops_generic;
57 mac->ops.setup_led = e1000_null_ops_generic;
58 mac->ops.blink_led = e1000_null_ops_generic;
59 mac->ops.led_on = e1000_null_ops_generic;
60 mac->ops.led_off = e1000_null_ops_generic;
61 /* LINK */
62 mac->ops.setup_link = e1000_null_ops_generic;
63 mac->ops.get_link_up_info = e1000_null_link_info;
64 mac->ops.check_for_link = e1000_null_ops_generic;
65 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
66 /* Management */
67 mac->ops.check_mng_mode = e1000_null_mng_mode;
68 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
69 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
70 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
71 /* VLAN, MC, etc. */
72 mac->ops.update_mc_addr_list = e1000_null_update_mc;
73 mac->ops.clear_vfta = e1000_null_mac_generic;
74 mac->ops.write_vfta = e1000_null_write_vfta;
75 mac->ops.rar_set = e1000_rar_set_generic;
76 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
77 }
78
79 /**
80 * e1000_null_ops_generic - No-op function, returns 0
81 * @hw: pointer to the HW structure
82 **/
83 s32 e1000_null_ops_generic(struct e1000_hw *hw)
84 {
85 DEBUGFUNC("e1000_null_ops_generic");
86 return E1000_SUCCESS;
87 }
88
89 /**
90 * e1000_null_mac_generic - No-op function, return void
91 * @hw: pointer to the HW structure
92 **/
93 void e1000_null_mac_generic(struct e1000_hw *hw)
94 {
95 DEBUGFUNC("e1000_null_mac_generic");
96 return;
97 }
98
99 /**
100 * e1000_null_link_info - No-op function, return 0
101 * @hw: pointer to the HW structure
102 **/
103 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
104 {
105 DEBUGFUNC("e1000_null_link_info");
106 return E1000_SUCCESS;
107 }
108
109 /**
110 * e1000_null_mng_mode - No-op function, return false
111 * @hw: pointer to the HW structure
112 **/
113 bool e1000_null_mng_mode(struct e1000_hw *hw)
114 {
115 DEBUGFUNC("e1000_null_mng_mode");
116 return false;
117 }
118
119 /**
120 * e1000_null_update_mc - No-op function, return void
121 * @hw: pointer to the HW structure
122 **/
123 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
124 {
125 DEBUGFUNC("e1000_null_update_mc");
126 return;
127 }
128
129 /**
130 * e1000_null_write_vfta - No-op function, return void
131 * @hw: pointer to the HW structure
132 **/
133 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
134 {
135 DEBUGFUNC("e1000_null_write_vfta");
136 return;
137 }
138
139 /**
140 * e1000_null_rar_set - No-op function, return void
141 * @hw: pointer to the HW structure
142 **/
143 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
144 {
145 DEBUGFUNC("e1000_null_rar_set");
146 return;
147 }
148
149 /**
150 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
151 * @hw: pointer to the HW structure
152 *
153 * Determines and stores the system bus information for a particular
154 * network interface. The following bus information is determined and stored:
155 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
156 **/
157 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
158 {
159 struct e1000_mac_info *mac = &hw->mac;
160 struct e1000_bus_info *bus = &hw->bus;
161 u32 status = E1000_READ_REG(hw, E1000_STATUS);
162 s32 ret_val = E1000_SUCCESS;
163
164 DEBUGFUNC("e1000_get_bus_info_pci_generic");
165
166 /* PCI or PCI-X? */
167 bus->type = (status & E1000_STATUS_PCIX_MODE)
168 ? e1000_bus_type_pcix
169 : e1000_bus_type_pci;
170
171 /* Bus speed */
172 if (bus->type == e1000_bus_type_pci) {
173 bus->speed = (status & E1000_STATUS_PCI66)
174 ? e1000_bus_speed_66
175 : e1000_bus_speed_33;
176 } else {
177 switch (status & E1000_STATUS_PCIX_SPEED) {
178 case E1000_STATUS_PCIX_SPEED_66:
179 bus->speed = e1000_bus_speed_66;
180 break;
181 case E1000_STATUS_PCIX_SPEED_100:
182 bus->speed = e1000_bus_speed_100;
183 break;
184 case E1000_STATUS_PCIX_SPEED_133:
185 bus->speed = e1000_bus_speed_133;
186 break;
187 default:
188 bus->speed = e1000_bus_speed_reserved;
189 break;
190 }
191 }
192
193 /* Bus width */
194 bus->width = (status & E1000_STATUS_BUS64)
195 ? e1000_bus_width_64
196 : e1000_bus_width_32;
197
198 /* Which PCI(-X) function? */
199 mac->ops.set_lan_id(hw);
200
201 return ret_val;
202 }
203
204 /**
205 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
206 * @hw: pointer to the HW structure
207 *
208 * Determines and stores the system bus information for a particular
209 * network interface. The following bus information is determined and stored:
210 * bus speed, bus width, type (PCIe), and PCIe function.
211 **/
212 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
213 {
214 struct e1000_mac_info *mac = &hw->mac;
215 struct e1000_bus_info *bus = &hw->bus;
216 s32 ret_val;
217 u16 pcie_link_status;
218
219 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
220
221 bus->type = e1000_bus_type_pci_express;
222
223 ret_val = e1000_read_pcie_cap_reg(hw,
224 PCIE_LINK_STATUS,
225 &pcie_link_status);
226 if (ret_val) {
227 bus->width = e1000_bus_width_unknown;
228 bus->speed = e1000_bus_speed_unknown;
229 } else {
230 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
231 case PCIE_LINK_SPEED_2500:
232 bus->speed = e1000_bus_speed_2500;
233 break;
234 case PCIE_LINK_SPEED_5000:
235 bus->speed = e1000_bus_speed_5000;
236 break;
237 default:
238 bus->speed = e1000_bus_speed_unknown;
239 break;
240 }
241
242 bus->width = (enum e1000_bus_width)((pcie_link_status &
243 PCIE_LINK_WIDTH_MASK) >>
244 PCIE_LINK_WIDTH_SHIFT);
245 }
246
247 mac->ops.set_lan_id(hw);
248
249 return E1000_SUCCESS;
250 }
251
252 /**
253 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
254 *
255 * @hw: pointer to the HW structure
256 *
257 * Determines the LAN function id by reading memory-mapped registers
258 * and swaps the port value if requested.
259 **/
260 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
261 {
262 struct e1000_bus_info *bus = &hw->bus;
263 u32 reg;
264
265 /*
266 * The status register reports the correct function number
267 * for the device regardless of function swap state.
268 */
269 reg = E1000_READ_REG(hw, E1000_STATUS);
270 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
271 }
272
273 /**
274 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
275 * @hw: pointer to the HW structure
276 *
277 * Determines the LAN function id by reading PCI config space.
278 **/
279 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
280 {
281 struct e1000_bus_info *bus = &hw->bus;
282 u16 pci_header_type;
283 u32 status;
284
285 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
286 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
287 status = E1000_READ_REG(hw, E1000_STATUS);
288 bus->func = (status & E1000_STATUS_FUNC_MASK)
289 >> E1000_STATUS_FUNC_SHIFT;
290 } else {
291 bus->func = 0;
292 }
293 }
294
295 /**
296 * e1000_set_lan_id_single_port - Set LAN id for a single port device
297 * @hw: pointer to the HW structure
298 *
299 * Sets the LAN function id to zero for a single port device.
300 **/
301 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
302 {
303 struct e1000_bus_info *bus = &hw->bus;
304
305 bus->func = 0;
306 }
307
308 /**
309 * e1000_clear_vfta_generic - Clear VLAN filter table
310 * @hw: pointer to the HW structure
311 *
312 * Clears the register array which contains the VLAN filter table by
313 * setting all the values to 0.
314 **/
315 void e1000_clear_vfta_generic(struct e1000_hw *hw)
316 {
317 u32 offset;
318
319 DEBUGFUNC("e1000_clear_vfta_generic");
320
321 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
322 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
323 E1000_WRITE_FLUSH(hw);
324 }
325 }
326
327 /**
328 * e1000_write_vfta_generic - Write value to VLAN filter table
329 * @hw: pointer to the HW structure
330 * @offset: register offset in VLAN filter table
331 * @value: register value written to VLAN filter table
332 *
333 * Writes value at the given offset in the register array which stores
334 * the VLAN filter table.
335 **/
336 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
337 {
338 DEBUGFUNC("e1000_write_vfta_generic");
339
340 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
341 E1000_WRITE_FLUSH(hw);
342 }
343
344 /**
345 * e1000_init_rx_addrs_generic - Initialize receive address's
346 * @hw: pointer to the HW structure
347 * @rar_count: receive address registers
348 *
349 * Setup the receive address registers by setting the base receive address
350 * register to the devices MAC address and clearing all the other receive
351 * address registers to 0.
352 **/
353 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
354 {
355 u32 i;
356 u8 mac_addr[ETH_ADDR_LEN] = {0};
357
358 DEBUGFUNC("e1000_init_rx_addrs_generic");
359
360 /* Setup the receive address */
361 DEBUGOUT("Programming MAC Address into RAR[0]\n");
362
363 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
364
365 /* Zero out the other (rar_entry_count - 1) receive addresses */
366 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
367 for (i = 1; i < rar_count; i++)
368 hw->mac.ops.rar_set(hw, mac_addr, i);
369 }
370
371 /**
372 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
373 * @hw: pointer to the HW structure
374 *
375 * Checks the nvm for an alternate MAC address. An alternate MAC address
376 * can be setup by pre-boot software and must be treated like a permanent
377 * address and must override the actual permanent MAC address. If an
378 * alternate MAC address is found it is programmed into RAR0, replacing
379 * the permanent address that was installed into RAR0 by the Si on reset.
380 * This function will return SUCCESS unless it encounters an error while
381 * reading the EEPROM.
382 **/
383 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
384 {
385 u32 i;
386 s32 ret_val = E1000_SUCCESS;
387 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
388 u8 alt_mac_addr[ETH_ADDR_LEN];
389
390 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
391
392 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
393 if (ret_val)
394 goto out;
395
396
397 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
398 &nvm_alt_mac_addr_offset);
399 if (ret_val) {
400 DEBUGOUT("NVM Read Error\n");
401 goto out;
402 }
403
404 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
405 (nvm_alt_mac_addr_offset == 0x0000))
406 /* There is no Alternate MAC Address */
407 goto out;
408
409 if (hw->bus.func == E1000_FUNC_1)
410 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
411 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
412 offset = nvm_alt_mac_addr_offset + (i >> 1);
413 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
414 if (ret_val) {
415 DEBUGOUT("NVM Read Error\n");
416 goto out;
417 }
418
419 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
420 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
421 }
422
423 /* if multicast bit is set, the alternate address will not be used */
424 if (alt_mac_addr[0] & 0x01) {
425 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
426 goto out;
427 }
428
429 /*
430 * We have a valid alternate MAC address, and we want to treat it the
431 * same as the normal permanent MAC address stored by the HW into the
432 * RAR. Do this by mapping this address into RAR0.
433 */
434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
435
436 out:
437 return ret_val;
438 }
439
440 /**
441 * e1000_rar_set_generic - Set receive address register
442 * @hw: pointer to the HW structure
443 * @addr: pointer to the receive address
444 * @index: receive address array register
445 *
446 * Sets the receive address array register at index to the address passed
447 * in by addr.
448 **/
449 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
450 {
451 u32 rar_low, rar_high;
452
453 DEBUGFUNC("e1000_rar_set_generic");
454
455 /*
456 * HW expects these in little endian so we reverse the byte order
457 * from network order (big endian) to little endian
458 */
459 rar_low = ((u32) addr[0] |
460 ((u32) addr[1] << 8) |
461 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
462
463 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
464
465 /* If MAC address zero, no need to set the AV bit */
466 if (rar_low || rar_high)
467 rar_high |= E1000_RAH_AV;
468
469 /*
470 * Some bridges will combine consecutive 32-bit writes into
471 * a single burst write, which will malfunction on some parts.
472 * The flushes avoid this.
473 */
474 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
475 E1000_WRITE_FLUSH(hw);
476 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
477 E1000_WRITE_FLUSH(hw);
478 }
479
480 /**
481 * e1000_update_mc_addr_list_generic - Update Multicast addresses
482 * @hw: pointer to the HW structure
483 * @mc_addr_list: array of multicast addresses to program
484 * @mc_addr_count: number of multicast addresses to program
485 *
486 * Updates entire Multicast Table Array.
487 * The caller must have a packed mc_addr_list of multicast addresses.
488 **/
489 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
490 u8 *mc_addr_list, u32 mc_addr_count)
491 {
492 u32 hash_value, hash_bit, hash_reg;
493 int i;
494
495 DEBUGFUNC("e1000_update_mc_addr_list_generic");
496
497 /* clear mta_shadow */
498 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
499
500 /* update mta_shadow from mc_addr_list */
501 for (i = 0; (u32) i < mc_addr_count; i++) {
502 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
503
504 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
505 hash_bit = hash_value & 0x1F;
506
507 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
508 mc_addr_list += (ETH_ADDR_LEN);
509 }
510
511 /* replace the entire MTA table */
512 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
513 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
514 E1000_WRITE_FLUSH(hw);
515 }
516
517 /**
518 * e1000_hash_mc_addr_generic - Generate a multicast hash value
519 * @hw: pointer to the HW structure
520 * @mc_addr: pointer to a multicast address
521 *
522 * Generates a multicast address hash value which is used to determine
523 * the multicast filter table array address and new table value.
524 **/
525 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
526 {
527 u32 hash_value, hash_mask;
528 u8 bit_shift = 0;
529
530 DEBUGFUNC("e1000_hash_mc_addr_generic");
531
532 /* Register count multiplied by bits per register */
533 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
534
535 /*
536 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
537 * where 0xFF would still fall within the hash mask.
538 */
539 while (hash_mask >> bit_shift != 0xFF)
540 bit_shift++;
541
542 /*
543 * The portion of the address that is used for the hash table
544 * is determined by the mc_filter_type setting.
545 * The algorithm is such that there is a total of 8 bits of shifting.
546 * The bit_shift for a mc_filter_type of 0 represents the number of
547 * left-shifts where the MSB of mc_addr[5] would still fall within
548 * the hash_mask. Case 0 does this exactly. Since there are a total
549 * of 8 bits of shifting, then mc_addr[4] will shift right the
550 * remaining number of bits. Thus 8 - bit_shift. The rest of the
551 * cases are a variation of this algorithm...essentially raising the
552 * number of bits to shift mc_addr[5] left, while still keeping the
553 * 8-bit shifting total.
554 *
555 * For example, given the following Destination MAC Address and an
556 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
557 * we can see that the bit_shift for case 0 is 4. These are the hash
558 * values resulting from each mc_filter_type...
559 * [0] [1] [2] [3] [4] [5]
560 * 01 AA 00 12 34 56
561 * LSB MSB
562 *
563 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
564 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
565 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
566 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
567 */
568 switch (hw->mac.mc_filter_type) {
569 default:
570 case 0:
571 break;
572 case 1:
573 bit_shift += 1;
574 break;
575 case 2:
576 bit_shift += 2;
577 break;
578 case 3:
579 bit_shift += 4;
580 break;
581 }
582
583 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
584 (((u16) mc_addr[5]) << bit_shift)));
585
586 return hash_value;
587 }
588
589 /**
590 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
591 * @hw: pointer to the HW structure
592 *
593 * In certain situations, a system BIOS may report that the PCIx maximum
594 * memory read byte count (MMRBC) value is higher than than the actual
595 * value. We check the PCIx command register with the current PCIx status
596 * register.
597 **/
598 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
599 {
600 u16 cmd_mmrbc;
601 u16 pcix_cmd;
602 u16 pcix_stat_hi_word;
603 u16 stat_mmrbc;
604
605 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
606
607 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
608 if (hw->bus.type != e1000_bus_type_pcix)
609 return;
610
611 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
612 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
613 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
614 PCIX_COMMAND_MMRBC_SHIFT;
615 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
616 PCIX_STATUS_HI_MMRBC_SHIFT;
617 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
618 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
619 if (cmd_mmrbc > stat_mmrbc) {
620 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
621 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
622 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
623 }
624 }
625
626 /**
627 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
628 * @hw: pointer to the HW structure
629 *
630 * Clears the base hardware counters by reading the counter registers.
631 **/
632 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
633 {
634 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
635
636 E1000_READ_REG(hw, E1000_CRCERRS);
637 E1000_READ_REG(hw, E1000_SYMERRS);
638 E1000_READ_REG(hw, E1000_MPC);
639 E1000_READ_REG(hw, E1000_SCC);
640 E1000_READ_REG(hw, E1000_ECOL);
641 E1000_READ_REG(hw, E1000_MCC);
642 E1000_READ_REG(hw, E1000_LATECOL);
643 E1000_READ_REG(hw, E1000_COLC);
644 E1000_READ_REG(hw, E1000_DC);
645 E1000_READ_REG(hw, E1000_SEC);
646 E1000_READ_REG(hw, E1000_RLEC);
647 E1000_READ_REG(hw, E1000_XONRXC);
648 E1000_READ_REG(hw, E1000_XONTXC);
649 E1000_READ_REG(hw, E1000_XOFFRXC);
650 E1000_READ_REG(hw, E1000_XOFFTXC);
651 E1000_READ_REG(hw, E1000_FCRUC);
652 E1000_READ_REG(hw, E1000_GPRC);
653 E1000_READ_REG(hw, E1000_BPRC);
654 E1000_READ_REG(hw, E1000_MPRC);
655 E1000_READ_REG(hw, E1000_GPTC);
656 E1000_READ_REG(hw, E1000_GORCL);
657 E1000_READ_REG(hw, E1000_GORCH);
658 E1000_READ_REG(hw, E1000_GOTCL);
659 E1000_READ_REG(hw, E1000_GOTCH);
660 E1000_READ_REG(hw, E1000_RNBC);
661 E1000_READ_REG(hw, E1000_RUC);
662 E1000_READ_REG(hw, E1000_RFC);
663 E1000_READ_REG(hw, E1000_ROC);
664 E1000_READ_REG(hw, E1000_RJC);
665 E1000_READ_REG(hw, E1000_TORL);
666 E1000_READ_REG(hw, E1000_TORH);
667 E1000_READ_REG(hw, E1000_TOTL);
668 E1000_READ_REG(hw, E1000_TOTH);
669 E1000_READ_REG(hw, E1000_TPR);
670 E1000_READ_REG(hw, E1000_TPT);
671 E1000_READ_REG(hw, E1000_MPTC);
672 E1000_READ_REG(hw, E1000_BPTC);
673 }
674
675 /**
676 * e1000_check_for_copper_link_generic - Check for link (Copper)
677 * @hw: pointer to the HW structure
678 *
679 * Checks to see of the link status of the hardware has changed. If a
680 * change in link status has been detected, then we read the PHY registers
681 * to get the current speed/duplex if link exists.
682 **/
683 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
684 {
685 struct e1000_mac_info *mac = &hw->mac;
686 s32 ret_val;
687 bool link;
688
689 DEBUGFUNC("e1000_check_for_copper_link");
690
691 /*
692 * We only want to go out to the PHY registers to see if Auto-Neg
693 * has completed and/or if our link status has changed. The
694 * get_link_status flag is set upon receiving a Link Status
695 * Change or Rx Sequence Error interrupt.
696 */
697 if (!mac->get_link_status) {
698 ret_val = E1000_SUCCESS;
699 goto out;
700 }
701
702 /*
703 * First we want to see if the MII Status Register reports
704 * link. If so, then we want to get the current speed/duplex
705 * of the PHY.
706 */
707 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
708 if (ret_val)
709 goto out;
710
711 if (!link)
712 goto out; /* No link detected */
713
714 mac->get_link_status = false;
715
716 /*
717 * Check if there was DownShift, must be checked
718 * immediately after link-up
719 */
720 e1000_check_downshift_generic(hw);
721
722 /*
723 * If we are forcing speed/duplex, then we simply return since
724 * we have already determined whether we have link or not.
725 */
726 if (!mac->autoneg) {
727 ret_val = -E1000_ERR_CONFIG;
728 goto out;
729 }
730
731 /*
732 * Auto-Neg is enabled. Auto Speed Detection takes care
733 * of MAC speed/duplex configuration. So we only need to
734 * configure Collision Distance in the MAC.
735 */
736 mac->ops.config_collision_dist(hw);
737
738 /*
739 * Configure Flow Control now that Auto-Neg has completed.
740 * First, we need to restore the desired flow control
741 * settings because we may have had to re-autoneg with a
742 * different link partner.
743 */
744 ret_val = e1000_config_fc_after_link_up_generic(hw);
745 if (ret_val)
746 DEBUGOUT("Error configuring flow control\n");
747
748 out:
749 return ret_val;
750 }
751
752 /**
753 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
754 * @hw: pointer to the HW structure
755 *
756 * Checks for link up on the hardware. If link is not up and we have
757 * a signal, then we need to force link up.
758 **/
759 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
760 {
761 struct e1000_mac_info *mac = &hw->mac;
762 u32 rxcw;
763 u32 ctrl;
764 u32 status;
765 s32 ret_val = E1000_SUCCESS;
766
767 DEBUGFUNC("e1000_check_for_fiber_link_generic");
768
769 ctrl = E1000_READ_REG(hw, E1000_CTRL);
770 status = E1000_READ_REG(hw, E1000_STATUS);
771 rxcw = E1000_READ_REG(hw, E1000_RXCW);
772
773 /*
774 * If we don't have link (auto-negotiation failed or link partner
775 * cannot auto-negotiate), the cable is plugged in (we have signal),
776 * and our link partner is not trying to auto-negotiate with us (we
777 * are receiving idles or data), we need to force link up. We also
778 * need to give auto-negotiation time to complete, in case the cable
779 * was just plugged in. The autoneg_failed flag does this.
780 */
781 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
782 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
783 (!(rxcw & E1000_RXCW_C))) {
784 if (mac->autoneg_failed == 0) {
785 mac->autoneg_failed = 1;
786 goto out;
787 }
788 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
789
790 /* Disable auto-negotiation in the TXCW register */
791 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
792
793 /* Force link-up and also force full-duplex. */
794 ctrl = E1000_READ_REG(hw, E1000_CTRL);
795 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
796 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
797
798 /* Configure Flow Control after forcing link up. */
799 ret_val = e1000_config_fc_after_link_up_generic(hw);
800 if (ret_val) {
801 DEBUGOUT("Error configuring flow control\n");
802 goto out;
803 }
804 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
805 /*
806 * If we are forcing link and we are receiving /C/ ordered
807 * sets, re-enable auto-negotiation in the TXCW register
808 * and disable forced link in the Device Control register
809 * in an attempt to auto-negotiate with our link partner.
810 */
811 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
812 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
813 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
814
815 mac->serdes_has_link = true;
816 }
817
818 out:
819 return ret_val;
820 }
821
822 /**
823 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
824 * @hw: pointer to the HW structure
825 *
826 * Checks for link up on the hardware. If link is not up and we have
827 * a signal, then we need to force link up.
828 **/
829 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
830 {
831 struct e1000_mac_info *mac = &hw->mac;
832 u32 rxcw;
833 u32 ctrl;
834 u32 status;
835 s32 ret_val = E1000_SUCCESS;
836
837 DEBUGFUNC("e1000_check_for_serdes_link_generic");
838
839 ctrl = E1000_READ_REG(hw, E1000_CTRL);
840 status = E1000_READ_REG(hw, E1000_STATUS);
841 rxcw = E1000_READ_REG(hw, E1000_RXCW);
842
843 /*
844 * If we don't have link (auto-negotiation failed or link partner
845 * cannot auto-negotiate), and our link partner is not trying to
846 * auto-negotiate with us (we are receiving idles or data),
847 * we need to force link up. We also need to give auto-negotiation
848 * time to complete.
849 */
850 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
851 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
852 if (mac->autoneg_failed == 0) {
853 mac->autoneg_failed = 1;
854 goto out;
855 }
856 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
857
858 /* Disable auto-negotiation in the TXCW register */
859 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
860
861 /* Force link-up and also force full-duplex. */
862 ctrl = E1000_READ_REG(hw, E1000_CTRL);
863 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
864 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
865
866 /* Configure Flow Control after forcing link up. */
867 ret_val = e1000_config_fc_after_link_up_generic(hw);
868 if (ret_val) {
869 DEBUGOUT("Error configuring flow control\n");
870 goto out;
871 }
872 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
873 /*
874 * If we are forcing link and we are receiving /C/ ordered
875 * sets, re-enable auto-negotiation in the TXCW register
876 * and disable forced link in the Device Control register
877 * in an attempt to auto-negotiate with our link partner.
878 */
879 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
880 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
881 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
882
883 mac->serdes_has_link = true;
884 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
885 /*
886 * If we force link for non-auto-negotiation switch, check
887 * link status based on MAC synchronization for internal
888 * serdes media type.
889 */
890 /* SYNCH bit and IV bit are sticky. */
891 usec_delay(10);
892 rxcw = E1000_READ_REG(hw, E1000_RXCW);
893 if (rxcw & E1000_RXCW_SYNCH) {
894 if (!(rxcw & E1000_RXCW_IV)) {
895 mac->serdes_has_link = true;
896 DEBUGOUT("SERDES: Link up - forced.\n");
897 }
898 } else {
899 mac->serdes_has_link = false;
900 DEBUGOUT("SERDES: Link down - force failed.\n");
901 }
902 }
903
904 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
905 status = E1000_READ_REG(hw, E1000_STATUS);
906 if (status & E1000_STATUS_LU) {
907 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
908 usec_delay(10);
909 rxcw = E1000_READ_REG(hw, E1000_RXCW);
910 if (rxcw & E1000_RXCW_SYNCH) {
911 if (!(rxcw & E1000_RXCW_IV)) {
912 mac->serdes_has_link = true;
913 DEBUGOUT("SERDES: Link up - autoneg "
914 "completed sucessfully.\n");
915 } else {
916 mac->serdes_has_link = false;
917 DEBUGOUT("SERDES: Link down - invalid"
918 "codewords detected in autoneg.\n");
919 }
920 } else {
921 mac->serdes_has_link = false;
922 DEBUGOUT("SERDES: Link down - no sync.\n");
923 }
924 } else {
925 mac->serdes_has_link = false;
926 DEBUGOUT("SERDES: Link down - autoneg failed\n");
927 }
928 }
929
930 out:
931 return ret_val;
932 }
933
934 /**
935 * e1000_setup_link_generic - Setup flow control and link settings
936 * @hw: pointer to the HW structure
937 *
938 * Determines which flow control settings to use, then configures flow
939 * control. Calls the appropriate media-specific link configuration
940 * function. Assuming the adapter has a valid link partner, a valid link
941 * should be established. Assumes the hardware has previously been reset
942 * and the transmitter and receiver are not enabled.
943 **/
944 s32 e1000_setup_link_generic(struct e1000_hw *hw)
945 {
946 s32 ret_val = E1000_SUCCESS;
947
948 DEBUGFUNC("e1000_setup_link_generic");
949
950 /*
951 * In the case of the phy reset being blocked, we already have a link.
952 * We do not need to set it up again.
953 */
954 if (e1000_check_reset_block(hw))
955 goto out;
956
957 /*
958 * If requested flow control is set to default, set flow control
959 * based on the EEPROM flow control settings.
960 */
961 if (hw->fc.requested_mode == e1000_fc_default) {
962 ret_val = e1000_set_default_fc_generic(hw);
963 if (ret_val)
964 goto out;
965 }
966
967 /*
968 * Save off the requested flow control mode for use later. Depending
969 * on the link partner's capabilities, we may or may not use this mode.
970 */
971 hw->fc.current_mode = hw->fc.requested_mode;
972
973 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
974 hw->fc.current_mode);
975
976 /* Call the necessary media_type subroutine to configure the link. */
977 ret_val = hw->mac.ops.setup_physical_interface(hw);
978 if (ret_val)
979 goto out;
980
981 /*
982 * Initialize the flow control address, type, and PAUSE timer
983 * registers to their default values. This is done even if flow
984 * control is disabled, because it does not hurt anything to
985 * initialize these registers.
986 */
987 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
988 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
989 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
990 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
991
992 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
993
994 ret_val = e1000_set_fc_watermarks_generic(hw);
995
996 out:
997 return ret_val;
998 }
999
1000 /**
1001 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1002 * @hw: pointer to the HW structure
1003 *
1004 * Configures collision distance and flow control for fiber and serdes
1005 * links. Upon successful setup, poll for link.
1006 **/
1007 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1008 {
1009 struct e1000_mac_info *mac = &hw->mac;
1010 u32 ctrl;
1011 s32 ret_val = E1000_SUCCESS;
1012
1013 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1014
1015 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1016
1017 /* Take the link out of reset */
1018 ctrl &= ~E1000_CTRL_LRST;
1019
1020 mac->ops.config_collision_dist(hw);
1021
1022 ret_val = e1000_commit_fc_settings_generic(hw);
1023 if (ret_val)
1024 goto out;
1025
1026 /*
1027 * Since auto-negotiation is enabled, take the link out of reset (the
1028 * link will be in reset, because we previously reset the chip). This
1029 * will restart auto-negotiation. If auto-negotiation is successful
1030 * then the link-up status bit will be set and the flow control enable
1031 * bits (RFCE and TFCE) will be set according to their negotiated value.
1032 */
1033 DEBUGOUT("Auto-negotiation enabled\n");
1034
1035 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1036 E1000_WRITE_FLUSH(hw);
1037 msec_delay(1);
1038
1039 /*
1040 * For these adapters, the SW definable pin 1 is set when the optics
1041 * detect a signal. If we have a signal, then poll for a "Link-Up"
1042 * indication.
1043 */
1044 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1045 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1046 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1047 } else {
1048 DEBUGOUT("No signal detected\n");
1049 }
1050
1051 out:
1052 return ret_val;
1053 }
1054
1055 /**
1056 * e1000_config_collision_dist_generic - Configure collision distance
1057 * @hw: pointer to the HW structure
1058 *
1059 * Configures the collision distance to the default value and is used
1060 * during link setup.
1061 **/
1062 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1063 {
1064 u32 tctl;
1065
1066 DEBUGFUNC("e1000_config_collision_dist_generic");
1067
1068 tctl = E1000_READ_REG(hw, E1000_TCTL);
1069
1070 tctl &= ~E1000_TCTL_COLD;
1071 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1072
1073 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1074 E1000_WRITE_FLUSH(hw);
1075 }
1076
1077 /**
1078 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1079 * @hw: pointer to the HW structure
1080 *
1081 * Polls for link up by reading the status register, if link fails to come
1082 * up with auto-negotiation, then the link is forced if a signal is detected.
1083 **/
1084 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1085 {
1086 struct e1000_mac_info *mac = &hw->mac;
1087 u32 i, status;
1088 s32 ret_val = E1000_SUCCESS;
1089
1090 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1091
1092 /*
1093 * If we have a signal (the cable is plugged in, or assumed true for
1094 * serdes media) then poll for a "Link-Up" indication in the Device
1095 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1096 * seconds (Auto-negotiation should complete in less than 500
1097 * milliseconds even if the other end is doing it in SW).
1098 */
1099 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1100 msec_delay(10);
1101 status = E1000_READ_REG(hw, E1000_STATUS);
1102 if (status & E1000_STATUS_LU)
1103 break;
1104 }
1105 if (i == FIBER_LINK_UP_LIMIT) {
1106 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1107 mac->autoneg_failed = 1;
1108 /*
1109 * AutoNeg failed to achieve a link, so we'll call
1110 * mac->check_for_link. This routine will force the
1111 * link up if we detect a signal. This will allow us to
1112 * communicate with non-autonegotiating link partners.
1113 */
1114 ret_val = mac->ops.check_for_link(hw);
1115 if (ret_val) {
1116 DEBUGOUT("Error while checking for link\n");
1117 goto out;
1118 }
1119 mac->autoneg_failed = 0;
1120 } else {
1121 mac->autoneg_failed = 0;
1122 DEBUGOUT("Valid Link Found\n");
1123 }
1124
1125 out:
1126 return ret_val;
1127 }
1128
1129 /**
1130 * e1000_commit_fc_settings_generic - Configure flow control
1131 * @hw: pointer to the HW structure
1132 *
1133 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1134 * base on the flow control settings in e1000_mac_info.
1135 **/
1136 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1137 {
1138 struct e1000_mac_info *mac = &hw->mac;
1139 u32 txcw;
1140 s32 ret_val = E1000_SUCCESS;
1141
1142 DEBUGFUNC("e1000_commit_fc_settings_generic");
1143
1144 /*
1145 * Check for a software override of the flow control settings, and
1146 * setup the device accordingly. If auto-negotiation is enabled, then
1147 * software will have to set the "PAUSE" bits to the correct value in
1148 * the Transmit Config Word Register (TXCW) and re-start auto-
1149 * negotiation. However, if auto-negotiation is disabled, then
1150 * software will have to manually configure the two flow control enable
1151 * bits in the CTRL register.
1152 *
1153 * The possible values of the "fc" parameter are:
1154 * 0: Flow control is completely disabled
1155 * 1: Rx flow control is enabled (we can receive pause frames,
1156 * but not send pause frames).
1157 * 2: Tx flow control is enabled (we can send pause frames but we
1158 * do not support receiving pause frames).
1159 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1160 */
1161 switch (hw->fc.current_mode) {
1162 case e1000_fc_none:
1163 /* Flow control completely disabled by a software over-ride. */
1164 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1165 break;
1166 case e1000_fc_rx_pause:
1167 /*
1168 * Rx Flow control is enabled and Tx Flow control is disabled
1169 * by a software over-ride. Since there really isn't a way to
1170 * advertise that we are capable of Rx Pause ONLY, we will
1171 * advertise that we support both symmetric and asymmetric Rx
1172 * PAUSE. Later, we will disable the adapter's ability to send
1173 * PAUSE frames.
1174 */
1175 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1176 break;
1177 case e1000_fc_tx_pause:
1178 /*
1179 * Tx Flow control is enabled, and Rx Flow control is disabled,
1180 * by a software over-ride.
1181 */
1182 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1183 break;
1184 case e1000_fc_full:
1185 /*
1186 * Flow control (both Rx and Tx) is enabled by a software
1187 * over-ride.
1188 */
1189 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1190 break;
1191 default:
1192 DEBUGOUT("Flow control param set incorrectly\n");
1193 ret_val = -E1000_ERR_CONFIG;
1194 goto out;
1195 break;
1196 }
1197
1198 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1199 mac->txcw = txcw;
1200
1201 out:
1202 return ret_val;
1203 }
1204
1205 /**
1206 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1207 * @hw: pointer to the HW structure
1208 *
1209 * Sets the flow control high/low threshold (watermark) registers. If
1210 * flow control XON frame transmission is enabled, then set XON frame
1211 * transmission as well.
1212 **/
1213 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1214 {
1215 u32 fcrtl = 0, fcrth = 0;
1216
1217 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1218
1219 /*
1220 * Set the flow control receive threshold registers. Normally,
1221 * these registers will be set to a default threshold that may be
1222 * adjusted later by the driver's runtime code. However, if the
1223 * ability to transmit pause frames is not enabled, then these
1224 * registers will be set to 0.
1225 */
1226 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1227 /*
1228 * We need to set up the Receive Threshold high and low water
1229 * marks as well as (optionally) enabling the transmission of
1230 * XON frames.
1231 */
1232 fcrtl = hw->fc.low_water;
1233 if (hw->fc.send_xon)
1234 fcrtl |= E1000_FCRTL_XONE;
1235
1236 fcrth = hw->fc.high_water;
1237 }
1238 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1239 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1240
1241 return E1000_SUCCESS;
1242 }
1243
1244 /**
1245 * e1000_set_default_fc_generic - Set flow control default values
1246 * @hw: pointer to the HW structure
1247 *
1248 * Read the EEPROM for the default values for flow control and store the
1249 * values.
1250 **/
1251 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1252 {
1253 s32 ret_val = E1000_SUCCESS;
1254 u16 nvm_data;
1255
1256 DEBUGFUNC("e1000_set_default_fc_generic");
1257
1258 /*
1259 * Read and store word 0x0F of the EEPROM. This word contains bits
1260 * that determine the hardware's default PAUSE (flow control) mode,
1261 * a bit that determines whether the HW defaults to enabling or
1262 * disabling auto-negotiation, and the direction of the
1263 * SW defined pins. If there is no SW over-ride of the flow
1264 * control setting, then the variable hw->fc will
1265 * be initialized based on a value in the EEPROM.
1266 */
1267 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1268
1269 if (ret_val) {
1270 DEBUGOUT("NVM Read Error\n");
1271 goto out;
1272 }
1273
1274 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1275 hw->fc.requested_mode = e1000_fc_none;
1276 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1277 NVM_WORD0F_ASM_DIR)
1278 hw->fc.requested_mode = e1000_fc_tx_pause;
1279 else
1280 hw->fc.requested_mode = e1000_fc_full;
1281
1282 out:
1283 return ret_val;
1284 }
1285
1286 /**
1287 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1288 * @hw: pointer to the HW structure
1289 *
1290 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1291 * device control register to reflect the adapter settings. TFCE and RFCE
1292 * need to be explicitly set by software when a copper PHY is used because
1293 * autonegotiation is managed by the PHY rather than the MAC. Software must
1294 * also configure these bits when link is forced on a fiber connection.
1295 **/
1296 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1297 {
1298 u32 ctrl;
1299 s32 ret_val = E1000_SUCCESS;
1300
1301 DEBUGFUNC("e1000_force_mac_fc_generic");
1302
1303 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1304
1305 /*
1306 * Because we didn't get link via the internal auto-negotiation
1307 * mechanism (we either forced link or we got link via PHY
1308 * auto-neg), we have to manually enable/disable transmit an
1309 * receive flow control.
1310 *
1311 * The "Case" statement below enables/disable flow control
1312 * according to the "hw->fc.current_mode" parameter.
1313 *
1314 * The possible values of the "fc" parameter are:
1315 * 0: Flow control is completely disabled
1316 * 1: Rx flow control is enabled (we can receive pause
1317 * frames but not send pause frames).
1318 * 2: Tx flow control is enabled (we can send pause frames
1319 * frames but we do not receive pause frames).
1320 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1321 * other: No other values should be possible at this point.
1322 */
1323 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1324
1325 switch (hw->fc.current_mode) {
1326 case e1000_fc_none:
1327 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1328 break;
1329 case e1000_fc_rx_pause:
1330 ctrl &= (~E1000_CTRL_TFCE);
1331 ctrl |= E1000_CTRL_RFCE;
1332 break;
1333 case e1000_fc_tx_pause:
1334 ctrl &= (~E1000_CTRL_RFCE);
1335 ctrl |= E1000_CTRL_TFCE;
1336 break;
1337 case e1000_fc_full:
1338 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1339 break;
1340 default:
1341 DEBUGOUT("Flow control param set incorrectly\n");
1342 ret_val = -E1000_ERR_CONFIG;
1343 goto out;
1344 }
1345
1346 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1347
1348 out:
1349 return ret_val;
1350 }
1351
1352 /**
1353 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1354 * @hw: pointer to the HW structure
1355 *
1356 * Checks the status of auto-negotiation after link up to ensure that the
1357 * speed and duplex were not forced. If the link needed to be forced, then
1358 * flow control needs to be forced also. If auto-negotiation is enabled
1359 * and did not fail, then we configure flow control based on our link
1360 * partner.
1361 **/
1362 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1363 {
1364 struct e1000_mac_info *mac = &hw->mac;
1365 s32 ret_val = E1000_SUCCESS;
1366 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1367 u16 speed, duplex;
1368
1369 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1370
1371 /*
1372 * Check for the case where we have fiber media and auto-neg failed
1373 * so we had to force link. In this case, we need to force the
1374 * configuration of the MAC to match the "fc" parameter.
1375 */
1376 if (mac->autoneg_failed) {
1377 if (hw->phy.media_type == e1000_media_type_fiber ||
1378 hw->phy.media_type == e1000_media_type_internal_serdes)
1379 ret_val = e1000_force_mac_fc_generic(hw);
1380 } else {
1381 if (hw->phy.media_type == e1000_media_type_copper)
1382 ret_val = e1000_force_mac_fc_generic(hw);
1383 }
1384
1385 if (ret_val) {
1386 DEBUGOUT("Error forcing flow control settings\n");
1387 goto out;
1388 }
1389
1390 /*
1391 * Check for the case where we have copper media and auto-neg is
1392 * enabled. In this case, we need to check and see if Auto-Neg
1393 * has completed, and if so, how the PHY and link partner has
1394 * flow control configured.
1395 */
1396 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1397 /*
1398 * Read the MII Status Register and check to see if AutoNeg
1399 * has completed. We read this twice because this reg has
1400 * some "sticky" (latched) bits.
1401 */
1402 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1403 if (ret_val)
1404 goto out;
1405 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1406 if (ret_val)
1407 goto out;
1408
1409 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1410 DEBUGOUT("Copper PHY and Auto Neg "
1411 "has not completed.\n");
1412 goto out;
1413 }
1414
1415 /*
1416 * The AutoNeg process has completed, so we now need to
1417 * read both the Auto Negotiation Advertisement
1418 * Register (Address 4) and the Auto_Negotiation Base
1419 * Page Ability Register (Address 5) to determine how
1420 * flow control was negotiated.
1421 */
1422 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1423 &mii_nway_adv_reg);
1424 if (ret_val)
1425 goto out;
1426 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1427 &mii_nway_lp_ability_reg);
1428 if (ret_val)
1429 goto out;
1430
1431 /*
1432 * Two bits in the Auto Negotiation Advertisement Register
1433 * (Address 4) and two bits in the Auto Negotiation Base
1434 * Page Ability Register (Address 5) determine flow control
1435 * for both the PHY and the link partner. The following
1436 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1437 * 1999, describes these PAUSE resolution bits and how flow
1438 * control is determined based upon these settings.
1439 * NOTE: DC = Don't Care
1440 *
1441 * LOCAL DEVICE | LINK PARTNER
1442 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1443 *-------|---------|-------|---------|--------------------
1444 * 0 | 0 | DC | DC | e1000_fc_none
1445 * 0 | 1 | 0 | DC | e1000_fc_none
1446 * 0 | 1 | 1 | 0 | e1000_fc_none
1447 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1448 * 1 | 0 | 0 | DC | e1000_fc_none
1449 * 1 | DC | 1 | DC | e1000_fc_full
1450 * 1 | 1 | 0 | 0 | e1000_fc_none
1451 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1452 *
1453 * Are both PAUSE bits set to 1? If so, this implies
1454 * Symmetric Flow Control is enabled at both ends. The
1455 * ASM_DIR bits are irrelevant per the spec.
1456 *
1457 * For Symmetric Flow Control:
1458 *
1459 * LOCAL DEVICE | LINK PARTNER
1460 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1461 *-------|---------|-------|---------|--------------------
1462 * 1 | DC | 1 | DC | E1000_fc_full
1463 *
1464 */
1465 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1466 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1467 /*
1468 * Now we need to check if the user selected Rx ONLY
1469 * of pause frames. In this case, we had to advertise
1470 * FULL flow control because we could not advertise Rx
1471 * ONLY. Hence, we must now check to see if we need to
1472 * turn OFF the TRANSMISSION of PAUSE frames.
1473 */
1474 if (hw->fc.requested_mode == e1000_fc_full) {
1475 hw->fc.current_mode = e1000_fc_full;
1476 DEBUGOUT("Flow Control = FULL.\r\n");
1477 } else {
1478 hw->fc.current_mode = e1000_fc_rx_pause;
1479 DEBUGOUT("Flow Control = "
1480 "Rx PAUSE frames only.\r\n");
1481 }
1482 }
1483 /*
1484 * For receiving PAUSE frames ONLY.
1485 *
1486 * LOCAL DEVICE | LINK PARTNER
1487 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1488 *-------|---------|-------|---------|--------------------
1489 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1490 */
1491 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1492 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1493 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1494 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1495 hw->fc.current_mode = e1000_fc_tx_pause;
1496 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1497 }
1498 /*
1499 * For transmitting PAUSE frames ONLY.
1500 *
1501 * LOCAL DEVICE | LINK PARTNER
1502 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1503 *-------|---------|-------|---------|--------------------
1504 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1505 */
1506 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1507 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1508 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1509 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1510 hw->fc.current_mode = e1000_fc_rx_pause;
1511 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1512 } else {
1513 /*
1514 * Per the IEEE spec, at this point flow control
1515 * should be disabled.
1516 */
1517 hw->fc.current_mode = e1000_fc_none;
1518 DEBUGOUT("Flow Control = NONE.\r\n");
1519 }
1520
1521 /*
1522 * Now we need to do one last check... If we auto-
1523 * negotiated to HALF DUPLEX, flow control should not be
1524 * enabled per IEEE 802.3 spec.
1525 */
1526 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1527 if (ret_val) {
1528 DEBUGOUT("Error getting link speed and duplex\n");
1529 goto out;
1530 }
1531
1532 if (duplex == HALF_DUPLEX)
1533 hw->fc.current_mode = e1000_fc_none;
1534
1535 /*
1536 * Now we call a subroutine to actually force the MAC
1537 * controller to use the correct flow control settings.
1538 */
1539 ret_val = e1000_force_mac_fc_generic(hw);
1540 if (ret_val) {
1541 DEBUGOUT("Error forcing flow control settings\n");
1542 goto out;
1543 }
1544 }
1545
1546 out:
1547 return ret_val;
1548 }
1549
1550 /**
1551 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1552 * @hw: pointer to the HW structure
1553 * @speed: stores the current speed
1554 * @duplex: stores the current duplex
1555 *
1556 * Read the status register for the current speed/duplex and store the current
1557 * speed and duplex for copper connections.
1558 **/
1559 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1560 u16 *duplex)
1561 {
1562 u32 status;
1563
1564 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1565
1566 status = E1000_READ_REG(hw, E1000_STATUS);
1567 if (status & E1000_STATUS_SPEED_1000) {
1568 *speed = SPEED_1000;
1569 DEBUGOUT("1000 Mbs, ");
1570 } else if (status & E1000_STATUS_SPEED_100) {
1571 *speed = SPEED_100;
1572 DEBUGOUT("100 Mbs, ");
1573 } else {
1574 *speed = SPEED_10;
1575 DEBUGOUT("10 Mbs, ");
1576 }
1577
1578 if (status & E1000_STATUS_FD) {
1579 *duplex = FULL_DUPLEX;
1580 DEBUGOUT("Full Duplex\n");
1581 } else {
1582 *duplex = HALF_DUPLEX;
1583 DEBUGOUT("Half Duplex\n");
1584 }
1585
1586 return E1000_SUCCESS;
1587 }
1588
1589 /**
1590 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1591 * @hw: pointer to the HW structure
1592 * @speed: stores the current speed
1593 * @duplex: stores the current duplex
1594 *
1595 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1596 * for fiber/serdes links.
1597 **/
1598 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1599 u16 *speed, u16 *duplex)
1600 {
1601 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1602
1603 *speed = SPEED_1000;
1604 *duplex = FULL_DUPLEX;
1605
1606 return E1000_SUCCESS;
1607 }
1608
1609 /**
1610 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1611 * @hw: pointer to the HW structure
1612 *
1613 * Acquire the HW semaphore to access the PHY or NVM
1614 **/
1615 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1616 {
1617 u32 swsm;
1618 s32 ret_val = E1000_SUCCESS;
1619 s32 timeout = hw->nvm.word_size + 1;
1620 s32 i = 0;
1621
1622 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1623
1624 /* Get the SW semaphore */
1625 while (i < timeout) {
1626 swsm = E1000_READ_REG(hw, E1000_SWSM);
1627 if (!(swsm & E1000_SWSM_SMBI))
1628 break;
1629
1630 usec_delay(50);
1631 i++;
1632 }
1633
1634 if (i == timeout) {
1635 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1636 ret_val = -E1000_ERR_NVM;
1637 goto out;
1638 }
1639
1640 /* Get the FW semaphore. */
1641 for (i = 0; i < timeout; i++) {
1642 swsm = E1000_READ_REG(hw, E1000_SWSM);
1643 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1644
1645 /* Semaphore acquired if bit latched */
1646 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1647 break;
1648
1649 usec_delay(50);
1650 }
1651
1652 if (i == timeout) {
1653 /* Release semaphores */
1654 e1000_put_hw_semaphore_generic(hw);
1655 DEBUGOUT("Driver can't access the NVM\n");
1656 ret_val = -E1000_ERR_NVM;
1657 goto out;
1658 }
1659
1660 out:
1661 return ret_val;
1662 }
1663
1664 /**
1665 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1666 * @hw: pointer to the HW structure
1667 *
1668 * Release hardware semaphore used to access the PHY or NVM
1669 **/
1670 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1671 {
1672 u32 swsm;
1673
1674 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1675
1676 swsm = E1000_READ_REG(hw, E1000_SWSM);
1677
1678 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1679
1680 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1681 }
1682
1683 /**
1684 * e1000_get_auto_rd_done_generic - Check for auto read completion
1685 * @hw: pointer to the HW structure
1686 *
1687 * Check EEPROM for Auto Read done bit.
1688 **/
1689 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1690 {
1691 s32 i = 0;
1692 s32 ret_val = E1000_SUCCESS;
1693
1694 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1695
1696 while (i < AUTO_READ_DONE_TIMEOUT) {
1697 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1698 break;
1699 msec_delay(1);
1700 i++;
1701 }
1702
1703 if (i == AUTO_READ_DONE_TIMEOUT) {
1704 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1705 ret_val = -E1000_ERR_RESET;
1706 goto out;
1707 }
1708
1709 out:
1710 return ret_val;
1711 }
1712
1713 /**
1714 * e1000_valid_led_default_generic - Verify a valid default LED config
1715 * @hw: pointer to the HW structure
1716 * @data: pointer to the NVM (EEPROM)
1717 *
1718 * Read the EEPROM for the current default LED configuration. If the
1719 * LED configuration is not valid, set to a valid LED configuration.
1720 **/
1721 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1722 {
1723 s32 ret_val;
1724
1725 DEBUGFUNC("e1000_valid_led_default_generic");
1726
1727 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1728 if (ret_val) {
1729 DEBUGOUT("NVM Read Error\n");
1730 goto out;
1731 }
1732
1733 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1734 *data = ID_LED_DEFAULT;
1735
1736 out:
1737 return ret_val;
1738 }
1739
1740 /**
1741 * e1000_id_led_init_generic -
1742 * @hw: pointer to the HW structure
1743 *
1744 **/
1745 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1746 {
1747 struct e1000_mac_info *mac = &hw->mac;
1748 s32 ret_val;
1749 const u32 ledctl_mask = 0x000000FF;
1750 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1751 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1752 u16 data, i, temp;
1753 const u16 led_mask = 0x0F;
1754
1755 DEBUGFUNC("e1000_id_led_init_generic");
1756
1757 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1758 if (ret_val)
1759 goto out;
1760
1761 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1762 mac->ledctl_mode1 = mac->ledctl_default;
1763 mac->ledctl_mode2 = mac->ledctl_default;
1764
1765 for (i = 0; i < 4; i++) {
1766 temp = (data >> (i << 2)) & led_mask;
1767 switch (temp) {
1768 case ID_LED_ON1_DEF2:
1769 case ID_LED_ON1_ON2:
1770 case ID_LED_ON1_OFF2:
1771 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1772 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1773 break;
1774 case ID_LED_OFF1_DEF2:
1775 case ID_LED_OFF1_ON2:
1776 case ID_LED_OFF1_OFF2:
1777 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1778 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1779 break;
1780 default:
1781 /* Do nothing */
1782 break;
1783 }
1784 switch (temp) {
1785 case ID_LED_DEF1_ON2:
1786 case ID_LED_ON1_ON2:
1787 case ID_LED_OFF1_ON2:
1788 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1789 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1790 break;
1791 case ID_LED_DEF1_OFF2:
1792 case ID_LED_ON1_OFF2:
1793 case ID_LED_OFF1_OFF2:
1794 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1795 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1796 break;
1797 default:
1798 /* Do nothing */
1799 break;
1800 }
1801 }
1802
1803 out:
1804 return ret_val;
1805 }
1806
1807 /**
1808 * e1000_setup_led_generic - Configures SW controllable LED
1809 * @hw: pointer to the HW structure
1810 *
1811 * This prepares the SW controllable LED for use and saves the current state
1812 * of the LED so it can be later restored.
1813 **/
1814 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1815 {
1816 u32 ledctl;
1817 s32 ret_val = E1000_SUCCESS;
1818
1819 DEBUGFUNC("e1000_setup_led_generic");
1820
1821 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1822 ret_val = -E1000_ERR_CONFIG;
1823 goto out;
1824 }
1825
1826 if (hw->phy.media_type == e1000_media_type_fiber) {
1827 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1828 hw->mac.ledctl_default = ledctl;
1829 /* Turn off LED0 */
1830 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1831 E1000_LEDCTL_LED0_BLINK |
1832 E1000_LEDCTL_LED0_MODE_MASK);
1833 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1834 E1000_LEDCTL_LED0_MODE_SHIFT);
1835 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1836 } else if (hw->phy.media_type == e1000_media_type_copper) {
1837 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1838 }
1839
1840 out:
1841 return ret_val;
1842 }
1843
1844 /**
1845 * e1000_cleanup_led_generic - Set LED config to default operation
1846 * @hw: pointer to the HW structure
1847 *
1848 * Remove the current LED configuration and set the LED configuration
1849 * to the default value, saved from the EEPROM.
1850 **/
1851 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1852 {
1853 DEBUGFUNC("e1000_cleanup_led_generic");
1854
1855 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1856 return E1000_SUCCESS;
1857 }
1858
1859 /**
1860 * e1000_blink_led_generic - Blink LED
1861 * @hw: pointer to the HW structure
1862 *
1863 * Blink the LEDs which are set to be on.
1864 **/
1865 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1866 {
1867 u32 ledctl_blink = 0;
1868 u32 i;
1869
1870 DEBUGFUNC("e1000_blink_led_generic");
1871
1872 if (hw->phy.media_type == e1000_media_type_fiber) {
1873 /* always blink LED0 for PCI-E fiber */
1874 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1875 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1876 } else {
1877 /*
1878 * set the blink bit for each LED that's "on" (0x0E)
1879 * in ledctl_mode2
1880 */
1881 ledctl_blink = hw->mac.ledctl_mode2;
1882 for (i = 0; i < 4; i++)
1883 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1884 E1000_LEDCTL_MODE_LED_ON)
1885 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1886 (i * 8));
1887 }
1888
1889 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1890
1891 return E1000_SUCCESS;
1892 }
1893
1894 /**
1895 * e1000_led_on_generic - Turn LED on
1896 * @hw: pointer to the HW structure
1897 *
1898 * Turn LED on.
1899 **/
1900 s32 e1000_led_on_generic(struct e1000_hw *hw)
1901 {
1902 u32 ctrl;
1903
1904 DEBUGFUNC("e1000_led_on_generic");
1905
1906 switch (hw->phy.media_type) {
1907 case e1000_media_type_fiber:
1908 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1909 ctrl &= ~E1000_CTRL_SWDPIN0;
1910 ctrl |= E1000_CTRL_SWDPIO0;
1911 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1912 break;
1913 case e1000_media_type_copper:
1914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1915 break;
1916 default:
1917 break;
1918 }
1919
1920 return E1000_SUCCESS;
1921 }
1922
1923 /**
1924 * e1000_led_off_generic - Turn LED off
1925 * @hw: pointer to the HW structure
1926 *
1927 * Turn LED off.
1928 **/
1929 s32 e1000_led_off_generic(struct e1000_hw *hw)
1930 {
1931 u32 ctrl;
1932
1933 DEBUGFUNC("e1000_led_off_generic");
1934
1935 switch (hw->phy.media_type) {
1936 case e1000_media_type_fiber:
1937 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1938 ctrl |= E1000_CTRL_SWDPIN0;
1939 ctrl |= E1000_CTRL_SWDPIO0;
1940 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1941 break;
1942 case e1000_media_type_copper:
1943 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1944 break;
1945 default:
1946 break;
1947 }
1948
1949 return E1000_SUCCESS;
1950 }
1951
1952 /**
1953 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1954 * @hw: pointer to the HW structure
1955 * @no_snoop: bitmap of snoop events
1956 *
1957 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1958 **/
1959 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1960 {
1961 u32 gcr;
1962
1963 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1964
1965 if (hw->bus.type != e1000_bus_type_pci_express)
1966 goto out;
1967
1968 if (no_snoop) {
1969 gcr = E1000_READ_REG(hw, E1000_GCR);
1970 gcr &= ~(PCIE_NO_SNOOP_ALL);
1971 gcr |= no_snoop;
1972 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1973 }
1974 out:
1975 return;
1976 }
1977
1978 /**
1979 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1980 * @hw: pointer to the HW structure
1981 *
1982 * Returns E1000_SUCCESS if successful, else returns -10
1983 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1984 * the master requests to be disabled.
1985 *
1986 * Disables PCI-Express master access and verifies there are no pending
1987 * requests.
1988 **/
1989 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1990 {
1991 u32 ctrl;
1992 s32 timeout = MASTER_DISABLE_TIMEOUT;
1993 s32 ret_val = E1000_SUCCESS;
1994
1995 DEBUGFUNC("e1000_disable_pcie_master_generic");
1996
1997 if (hw->bus.type != e1000_bus_type_pci_express)
1998 goto out;
1999
2000 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2001 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2002 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2003
2004 while (timeout) {
2005 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2006 E1000_STATUS_GIO_MASTER_ENABLE))
2007 break;
2008 usec_delay(100);
2009 timeout--;
2010 }
2011
2012 if (!timeout) {
2013 DEBUGOUT("Master requests are pending.\n");
2014 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2015 }
2016
2017 out:
2018 return ret_val;
2019 }
2020
2021 /**
2022 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2023 * @hw: pointer to the HW structure
2024 *
2025 * Reset the Adaptive Interframe Spacing throttle to default values.
2026 **/
2027 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2028 {
2029 struct e1000_mac_info *mac = &hw->mac;
2030
2031 DEBUGFUNC("e1000_reset_adaptive_generic");
2032
2033 if (!mac->adaptive_ifs) {
2034 DEBUGOUT("Not in Adaptive IFS mode!\n");
2035 goto out;
2036 }
2037
2038 mac->current_ifs_val = 0;
2039 mac->ifs_min_val = IFS_MIN;
2040 mac->ifs_max_val = IFS_MAX;
2041 mac->ifs_step_size = IFS_STEP;
2042 mac->ifs_ratio = IFS_RATIO;
2043
2044 mac->in_ifs_mode = false;
2045 E1000_WRITE_REG(hw, E1000_AIT, 0);
2046 out:
2047 return;
2048 }
2049
2050 /**
2051 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2052 * @hw: pointer to the HW structure
2053 *
2054 * Update the Adaptive Interframe Spacing Throttle value based on the
2055 * time between transmitted packets and time between collisions.
2056 **/
2057 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2058 {
2059 struct e1000_mac_info *mac = &hw->mac;
2060
2061 DEBUGFUNC("e1000_update_adaptive_generic");
2062
2063 if (!mac->adaptive_ifs) {
2064 DEBUGOUT("Not in Adaptive IFS mode!\n");
2065 goto out;
2066 }
2067
2068 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2069 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2070 mac->in_ifs_mode = true;
2071 if (mac->current_ifs_val < mac->ifs_max_val) {
2072 if (!mac->current_ifs_val)
2073 mac->current_ifs_val = mac->ifs_min_val;
2074 else
2075 mac->current_ifs_val +=
2076 mac->ifs_step_size;
2077 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2078 }
2079 }
2080 } else {
2081 if (mac->in_ifs_mode &&
2082 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2083 mac->current_ifs_val = 0;
2084 mac->in_ifs_mode = false;
2085 E1000_WRITE_REG(hw, E1000_AIT, 0);
2086 }
2087 }
2088 out:
2089 return;
2090 }
2091
2092 /**
2093 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2094 * @hw: pointer to the HW structure
2095 *
2096 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2097 * set, which is forced to MDI mode only.
2098 **/
2099 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2100 {
2101 s32 ret_val = E1000_SUCCESS;
2102
2103 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2104
2105 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2106 DEBUGOUT("Invalid MDI setting detected\n");
2107 hw->phy.mdix = 1;
2108 ret_val = -E1000_ERR_CONFIG;
2109 goto out;
2110 }
2111
2112 out:
2113 return ret_val;
2114 }
Mirror of AROS' svn.