workbench/devs/networks/e1000/e1000_82542.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82542 Gigabit Ethernet Controller
  31  */
  32
  33 #include "e1000_api.h"
  34
  35 static s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
  36 static s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
  37 static s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
  38 static s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
  39 static s32  e1000_reset_hw_82542(struct e1000_hw *hw);
  40 static s32  e1000_init_hw_82542(struct e1000_hw *hw);
  41 static s32  e1000_setup_link_82542(struct e1000_hw *hw);
  42 static s32  e1000_led_on_82542(struct e1000_hw *hw);
  43 static s32  e1000_led_off_82542(struct e1000_hw *hw);
  44 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
  45 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
  46 static s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
  47
  48 /**
  49  *  e1000_init_phy_params_82542 - Init PHY func ptrs.
  50  *  @hw: pointer to the HW structure
  51  **/
  52 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
  53 {
  54         struct e1000_phy_info *phy = &hw->phy;
  55         s32 ret_val = E1000_SUCCESS;
  56
  57         DEBUGFUNC("e1000_init_phy_params_82542");
  58
  59         phy->type               = e1000_phy_none;
  60
  61         return ret_val;
  62 }
  63
  64 /**
  65  *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
  66  *  @hw: pointer to the HW structure
  67  **/
  68 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
  69 {
  70         struct e1000_nvm_info *nvm = &hw->nvm;
  71
  72         DEBUGFUNC("e1000_init_nvm_params_82542");
  73
  74         nvm->address_bits       =  6;
  75         nvm->delay_usec         = 50;
  76         nvm->opcode_bits        =  3;
  77         nvm->type               = e1000_nvm_eeprom_microwire;
  78         nvm->word_size          = 64;
  79
  80         /* Function Pointers */
  81         nvm->ops.read           = e1000_read_nvm_microwire;
  82         nvm->ops.release        = e1000_stop_nvm;
  83         nvm->ops.write          = e1000_write_nvm_microwire;
  84         nvm->ops.update         = e1000_update_nvm_checksum_generic;
  85         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
  86
  87         return E1000_SUCCESS;
  88 }
  89
  90 /**
  91  *  e1000_init_mac_params_82542 - Init MAC func ptrs.
  92  *  @hw: pointer to the HW structure
  93  **/
  94 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
  95 {
  96         struct e1000_mac_info *mac = &hw->mac;
  97
  98         DEBUGFUNC("e1000_init_mac_params_82542");
  99
 100         /* Set media type */
 101         hw->phy.media_type = e1000_media_type_fiber;
 102
 103         /* Set mta register count */
 104         mac->mta_reg_count = 128;
 105         /* Set rar entry count */
 106         mac->rar_entry_count = E1000_RAR_ENTRIES;
 107
 108         /* Function pointers */
 109
 110         /* bus type/speed/width */
 111         mac->ops.get_bus_info = e1000_get_bus_info_82542;
 112         /* function id */
 113         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 114         /* reset */
 115         mac->ops.reset_hw = e1000_reset_hw_82542;
 116         /* hw initialization */
 117         mac->ops.init_hw = e1000_init_hw_82542;
 118         /* link setup */
 119         mac->ops.setup_link = e1000_setup_link_82542;
 120         /* phy/fiber/serdes setup */
 121         mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
 122         /* check for link */
 123         mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 124         /* multicast address update */
 125         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 126         /* writing VFTA */
 127         mac->ops.write_vfta = e1000_write_vfta_generic;
 128         /* clearing VFTA */
 129         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 130         /* read mac address */
 131         mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
 132         /* set RAR */
 133         mac->ops.rar_set = e1000_rar_set_82542;
 134         /* turn on/off LED */
 135         mac->ops.led_on = e1000_led_on_82542;
 136         mac->ops.led_off = e1000_led_off_82542;
 137         /* clear hardware counters */
 138         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
 139         /* link info */
 140         mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
 141
 142         return E1000_SUCCESS;
 143 }
 144
 145 /**
 146  *  e1000_init_function_pointers_82542 - Init func ptrs.
 147  *  @hw: pointer to the HW structure
 148  *
 149  *  Called to initialize all function pointers and parameters.
 150  **/
 151 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
 152 {
 153         DEBUGFUNC("e1000_init_function_pointers_82542");
 154
 155         hw->mac.ops.init_params = e1000_init_mac_params_82542;
 156         hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
 157         hw->phy.ops.init_params = e1000_init_phy_params_82542;
 158 }
 159
 160 /**
 161  *  e1000_get_bus_info_82542 - Obtain bus information for adapter
 162  *  @hw: pointer to the HW structure
 163  *
 164  *  This will obtain information about the HW bus for which the
 165  *  adapter is attached and stores it in the hw structure.
 166  **/
 167 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
 168 {
 169         DEBUGFUNC("e1000_get_bus_info_82542");
 170
 171         hw->bus.type = e1000_bus_type_pci;
 172         hw->bus.speed = e1000_bus_speed_unknown;
 173         hw->bus.width = e1000_bus_width_unknown;
 174
 175         return E1000_SUCCESS;
 176 }
 177
 178 /**
 179  *  e1000_reset_hw_82542 - Reset hardware
 180  *  @hw: pointer to the HW structure
 181  *
 182  *  This resets the hardware into a known state.
 183  **/
 184 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
 185 {
 186         struct e1000_bus_info *bus = &hw->bus;
 187         s32 ret_val = E1000_SUCCESS;
 188         u32 ctrl;
 189
 190         DEBUGFUNC("e1000_reset_hw_82542");
 191
 192         if (hw->revision_id == E1000_REVISION_2) {
 193                 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
 194                 e1000_pci_clear_mwi(hw);
 195         }
 196
 197         DEBUGOUT("Masking off all interrupts\n");
 198         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 199
 200         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 201         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 202         E1000_WRITE_FLUSH(hw);
 203
 204         /*
 205          * Delay to allow any outstanding PCI transactions to complete before
 206          * resetting the device
 207          */
 208         msec_delay(10);
 209
 210         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 211
 212         DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
 213         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 214
 215         hw->nvm.ops.reload(hw);
 216         msec_delay(2);
 217
 218         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 219         E1000_READ_REG(hw, E1000_ICR);
 220
 221         if (hw->revision_id == E1000_REVISION_2) {
 222                 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 223                         e1000_pci_set_mwi(hw);
 224         }
 225
 226         return ret_val;
 227 }
 228
 229 /**
 230  *  e1000_init_hw_82542 - Initialize hardware
 231  *  @hw: pointer to the HW structure
 232  *
 233  *  This inits the hardware readying it for operation.
 234  **/
 235 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
 236 {
 237         struct e1000_mac_info *mac = &hw->mac;
 238         struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
 239         s32 ret_val = E1000_SUCCESS;
 240         u32 ctrl;
 241         u16 i;
 242
 243         DEBUGFUNC("e1000_init_hw_82542");
 244
 245         /* Disabling VLAN filtering */
 246         E1000_WRITE_REG(hw, E1000_VET, 0);
 247         mac->ops.clear_vfta(hw);
 248
 249         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 250         if (hw->revision_id == E1000_REVISION_2) {
 251                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 252                 e1000_pci_clear_mwi(hw);
 253                 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
 254                 E1000_WRITE_FLUSH(hw);
 255                 msec_delay(5);
 256         }
 257
 258         /* Setup the receive address. */
 259         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 260
 261         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 262         if (hw->revision_id == E1000_REVISION_2) {
 263                 E1000_WRITE_REG(hw, E1000_RCTL, 0);
 264                 E1000_WRITE_FLUSH(hw);
 265                 msec_delay(1);
 266                 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 267                         e1000_pci_set_mwi(hw);
 268         }
 269
 270         /* Zero out the Multicast HASH table */
 271         DEBUGOUT("Zeroing the MTA\n");
 272         for (i = 0; i < mac->mta_reg_count; i++)
 273                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 274
 275         /*
 276          * Set the PCI priority bit correctly in the CTRL register.  This
 277          * determines if the adapter gives priority to receives, or if it
 278          * gives equal priority to transmits and receives.
 279          */
 280         if (dev_spec->dma_fairness) {
 281                 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 282                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
 283         }
 284
 285         /* Setup link and flow control */
 286         ret_val = e1000_setup_link_82542(hw);
 287
 288         /*
 289          * Clear all of the statistics registers (clear on read).  It is
 290          * important that we do this after we have tried to establish link
 291          * because the symbol error count will increment wildly if there
 292          * is no link.
 293          */
 294         e1000_clear_hw_cntrs_82542(hw);
 295
 296         return ret_val;
 297 }
 298
 299 /**
 300  *  e1000_setup_link_82542 - Setup flow control and link settings
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Determines which flow control settings to use, then configures flow
 304  *  control.  Calls the appropriate media-specific link configuration
 305  *  function.  Assuming the adapter has a valid link partner, a valid link
 306  *  should be established.  Assumes the hardware has previously been reset
 307  *  and the transmitter and receiver are not enabled.
 308  **/
 309 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
 310 {
 311         struct e1000_mac_info *mac = &hw->mac;
 312         s32 ret_val = E1000_SUCCESS;
 313
 314         DEBUGFUNC("e1000_setup_link_82542");
 315
 316         ret_val = e1000_set_default_fc_generic(hw);
 317         if (ret_val)
 318                 goto out;
 319
 320         hw->fc.requested_mode &= ~e1000_fc_tx_pause;
 321
 322         if (mac->report_tx_early == 1)
 323                 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
 324
 325         /*
 326          * Save off the requested flow control mode for use later.  Depending
 327          * on the link partner's capabilities, we may or may not use this mode.
 328          */
 329         hw->fc.current_mode = hw->fc.requested_mode;
 330
 331         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
 332                                                      hw->fc.current_mode);
 333
 334         /* Call the necessary subroutine to configure the link. */
 335         ret_val = mac->ops.setup_physical_interface(hw);
 336         if (ret_val)
 337                 goto out;
 338
 339         /*
 340          * Initialize the flow control address, type, and PAUSE timer
 341          * registers to their default values.  This is done even if flow
 342          * control is disabled, because it does not hurt anything to
 343          * initialize these registers.
 344          */
 345         DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
 346
 347         E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 348         E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 349         E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
 350
 351         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
 352
 353         ret_val = e1000_set_fc_watermarks_generic(hw);
 354
 355 out:
 356         return ret_val;
 357 }
 358
 359 /**
 360  *  e1000_led_on_82542 - Turn on SW controllable LED
 361  *  @hw: pointer to the HW structure
 362  *
 363  *  Turns the SW defined LED on.
 364  **/
 365 static s32 e1000_led_on_82542(struct e1000_hw *hw)
 366 {
 367         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 368
 369         DEBUGFUNC("e1000_led_on_82542");
 370
 371         ctrl |= E1000_CTRL_SWDPIN0;
 372         ctrl |= E1000_CTRL_SWDPIO0;
 373         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 374
 375         return E1000_SUCCESS;
 376 }
 377
 378 /**
 379  *  e1000_led_off_82542 - Turn off SW controllable LED
 380  *  @hw: pointer to the HW structure
 381  *
 382  *  Turns the SW defined LED off.
 383  **/
 384 static s32 e1000_led_off_82542(struct e1000_hw *hw)
 385 {
 386         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 387
 388         DEBUGFUNC("e1000_led_off_82542");
 389
 390         ctrl &= ~E1000_CTRL_SWDPIN0;
 391         ctrl |= E1000_CTRL_SWDPIO0;
 392         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 393
 394         return E1000_SUCCESS;
 395 }
 396
 397 /**
 398  *  e1000_rar_set_82542 - Set receive address register
 399  *  @hw: pointer to the HW structure
 400  *  @addr: pointer to the receive address
 401  *  @index: receive address array register
 402  *
 403  *  Sets the receive address array register at index to the address passed
 404  *  in by addr.
 405  **/
 406 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
 407 {
 408         u32 rar_low, rar_high;
 409
 410         DEBUGFUNC("e1000_rar_set_82542");
 411
 412         /*
 413          * HW expects these in little endian so we reverse the byte order
 414          * from network order (big endian) to little endian
 415          */
 416         rar_low = ((u32) addr[0] |
 417                    ((u32) addr[1] << 8) |
 418                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 419
 420         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 421
 422         /* If MAC address zero, no need to set the AV bit */
 423         if (rar_low || rar_high)
 424                 rar_high |= E1000_RAH_AV;
 425
 426         E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
 427         E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
 428 }
 429
 430 /**
 431  *  e1000_translate_register_82542 - Translate the proper register offset
 432  *  @reg: e1000 register to be read
 433  *
 434  *  Registers in 82542 are located in different offsets than other adapters
 435  *  even though they function in the same manner.  This function takes in
 436  *  the name of the register to read and returns the correct offset for
 437  *  82542 silicon.
 438  **/
 439 u32 e1000_translate_register_82542(u32 reg)
 440 {
 441         /*
 442          * Some of the 82542 registers are located at different
 443          * offsets than they are in newer adapters.
 444          * Despite the difference in location, the registers
 445          * function in the same manner.
 446          */
 447         switch (reg) {
 448         case E1000_RA:
 449                 reg = 0x00040;
 450                 break;
 451         case E1000_RDTR:
 452                 reg = 0x00108;
 453                 break;
 454         case E1000_RDBAL(0):
 455                 reg = 0x00110;
 456                 break;
 457         case E1000_RDBAH(0):
 458                 reg = 0x00114;
 459                 break;
 460         case E1000_RDLEN(0):
 461                 reg = 0x00118;
 462                 break;
 463         case E1000_RDH(0):
 464                 reg = 0x00120;
 465                 break;
 466         case E1000_RDT(0):
 467                 reg = 0x00128;
 468                 break;
 469         case E1000_RDBAL(1):
 470                 reg = 0x00138;
 471                 break;
 472         case E1000_RDBAH(1):
 473                 reg = 0x0013C;
 474                 break;
 475         case E1000_RDLEN(1):
 476                 reg = 0x00140;
 477                 break;
 478         case E1000_RDH(1):
 479                 reg = 0x00148;
 480                 break;
 481         case E1000_RDT(1):
 482                 reg = 0x00150;
 483                 break;
 484         case E1000_FCRTH:
 485                 reg = 0x00160;
 486                 break;
 487         case E1000_FCRTL:
 488                 reg = 0x00168;
 489                 break;
 490         case E1000_MTA:
 491                 reg = 0x00200;
 492                 break;
 493         case E1000_TDBAL(0):
 494                 reg = 0x00420;
 495                 break;
 496         case E1000_TDBAH(0):
 497                 reg = 0x00424;
 498                 break;
 499         case E1000_TDLEN(0):
 500                 reg = 0x00428;
 501                 break;
 502         case E1000_TDH(0):
 503                 reg = 0x00430;
 504                 break;
 505         case E1000_TDT(0):
 506                 reg = 0x00438;
 507                 break;
 508         case E1000_TIDV:
 509                 reg = 0x00440;
 510                 break;
 511         case E1000_VFTA:
 512                 reg = 0x00600;
 513                 break;
 514         case E1000_TDFH:
 515                 reg = 0x08010;
 516                 break;
 517         case E1000_TDFT:
 518                 reg = 0x08018;
 519                 break;
 520         default:
 521                 break;
 522         }
 523
 524         return reg;
 525 }
 526
 527 /**
 528  *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
 529  *  @hw: pointer to the HW structure
 530  *
 531  *  Clears the hardware counters by reading the counter registers.
 532  **/
 533 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
 534 {
 535         DEBUGFUNC("e1000_clear_hw_cntrs_82542");
 536
 537         e1000_clear_hw_cntrs_base_generic(hw);
 538
 539         E1000_READ_REG(hw, E1000_PRC64);
 540         E1000_READ_REG(hw, E1000_PRC127);
 541         E1000_READ_REG(hw, E1000_PRC255);
 542         E1000_READ_REG(hw, E1000_PRC511);
 543         E1000_READ_REG(hw, E1000_PRC1023);
 544         E1000_READ_REG(hw, E1000_PRC1522);
 545         E1000_READ_REG(hw, E1000_PTC64);
 546         E1000_READ_REG(hw, E1000_PTC127);
 547         E1000_READ_REG(hw, E1000_PTC255);
 548         E1000_READ_REG(hw, E1000_PTC511);
 549         E1000_READ_REG(hw, E1000_PTC1023);
 550         E1000_READ_REG(hw, E1000_PTC1522);
 551 }
 552
 553 /**
 554  *  e1000_read_mac_addr_82542 - Read device MAC address
 555  *  @hw: pointer to the HW structure
 556  *
 557  *  Reads the device MAC address from the EEPROM and stores the value.
 558  **/
 559 s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
 560 {
 561         s32  ret_val = E1000_SUCCESS;
 562         u16 offset, nvm_data, i;
 563
 564         DEBUGFUNC("e1000_read_mac_addr");
 565
 566         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 567                 offset = i >> 1;
 568                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 569                 if (ret_val) {
 570                         DEBUGOUT("NVM Read Error\n");
 571                         goto out;
 572                 }
 573                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 574                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 575         }
 576
 577         for (i = 0; i < ETH_ADDR_LEN; i++)
 578                 hw->mac.addr[i] = hw->mac.perm_addr[i];
 579
 580 out:
 581         return ret_val;
 582 }