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[AROS.git] / workbench / devs / monitors / IntelGMA / 3D_blitter.c
blob6a593d779e77f84cd0feed3e6addc277c6f8b2e2
1 /*
2 Copyright © 2012-2017, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 /*
7 * Copyright © 2011 Intel Corporation
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
28 * Authors:
29 * Chris Wilson (intel-gpu-tools)
30 * 2012-2017, The AROS Development Team.
33 #include <proto/exec.h>
34 #include <hidd/gfx.h>
35 #include <aros/debug.h>
37 #include "intelgma_hidd.h"
38 #include "intelG45_regs.h"
40 //#include "i915/i915_reg.h" // crashes !?
41 #include "i915_reg.h"
43 #include "i915_3d.h"
46 extern struct g45staticdata sd;
47 #define sd ((struct g45staticdata*)&(sd))
50 static inline uint32_t pack_float(float f)
52 union {
53 uint32_t dw;
54 float f;
55 } u;
56 u.f = f;
57 return u.dw;
60 #define IS_915G(Id) ((Id) == 0x2582 || \
61 (Id) == 0x258a)
62 #define IS_915GM(Id) ((Id) == 0x2592)
64 #define IS_915(Id) (IS_915G(Id) || \
65 IS_915GM(Id))
67 #define IS_945G(Id) ((Id) == 0x2772)
68 #define IS_945GM(Id) ((Id) == 0x27A2 || \
69 (Id) == 0x27AE)
71 #define IS_945(Id) (IS_945G(Id) || \
72 IS_945GM(Id) || \
73 IS_G33(Id) || \
74 IS_PINEVIEW(Id))
76 #define IS_G33(Id) ((Id) == 0x29C2 || \
77 (Id) == 0x29B2 || \
78 (Id) == 0x29D2)
80 #define IS_PINEVIEW(Id) ((Id) == 0xa001 || \
81 (Id) == 0xa011)
83 #define IS_GEN3(Id) (IS_915(Id) || \
84 IS_945(Id) || \
85 IS_G33(Id) || \
86 IS_PINEVIEW(Id))
88 BOOL copybox3d_supported()
90 // supported chipsets
91 if( IS_GEN3( sd->ProductID ) )
93 return TRUE;
95 return FALSE;
98 BOOL copybox3d( GMABitMap_t *bm_dst, GMABitMap_t *bm_src,
99 ULONG dst_x,ULONG dst_y,ULONG dst_width, ULONG dst_height,
100 ULONG src_x,ULONG src_y,ULONG src_width, ULONG src_height )
102 uint32_t dst_format;
103 uint32_t src_format;
105 if( !copybox3d_supported() )
107 return FALSE;
110 // buffers in gfx memory ?
111 if( ! (bm_src->fbgfx && bm_src->fbgfx) )
113 return FALSE;
116 // Max texture size, src and dst must be differend (at least if overlaps)
117 if( bm_src->pitch/4 > 2048 || bm_src->height > 2048 || bm_dst == bm_src )
119 return FALSE;
122 // src pitch must be long aligmented.
123 if( bm_src->pitch & 0x3 )
125 bug("[GMA] copybox3d: ERROR bm_src->pitch=%d/n",bm_src->pitch);
126 return FALSE;
129 if(bm_src->bpp == 4)
131 src_format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
133 else if(bm_src->bpp == 2)
135 src_format = MAPSURF_16BIT | MT_16BIT_RGB565;
137 else
139 bug("[GMA] copybox3d: ERROR src_bpp=%d/n",bm_src->bpp);
140 return FALSE;
143 if(bm_dst->bpp == 4)
145 dst_format = COLR_BUF_ARGB8888;
147 else if(bm_dst->bpp == 2)
149 dst_format = COLR_BUF_RGB565;
151 else
153 bug("[GMA] copybox3d: ERROR dst_bpp=%d/n",bm_dst->bpp);
154 return FALSE;
157 LOCK_HW
158 START_RING(72);
160 /* invariant state */
161 OUT_RING( _3DSTATE_AA_CMD |
162 AA_LINE_ECAAR_WIDTH_ENABLE |
163 AA_LINE_ECAAR_WIDTH_1_0 |
164 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0 );
165 OUT_RING( _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
166 IAB_MODIFY_ENABLE |
167 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
168 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
169 IAB_SRC_FACTOR_SHIFT) |
170 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
171 IAB_DST_FACTOR_SHIFT) );
172 OUT_RING( _3DSTATE_DFLT_DIFFUSE_CMD );
173 OUT_RING( 0 );
174 OUT_RING( _3DSTATE_DFLT_SPEC_CMD );
175 OUT_RING( 0 );
176 OUT_RING( _3DSTATE_DFLT_Z_CMD );
177 OUT_RING( 0 );
178 OUT_RING( _3DSTATE_COORD_SET_BINDINGS |
179 CSB_TCB(0, 0) |
180 CSB_TCB(1, 1) |
181 CSB_TCB(2, 2) |
182 CSB_TCB(3, 3) |
183 CSB_TCB(4, 4) |
184 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7) );
185 OUT_RING( _3DSTATE_RASTER_RULES_CMD |
186 ENABLE_POINT_RASTER_RULE |
187 OGL_POINT_RASTER_RULE |
188 ENABLE_LINE_STRIP_PROVOKE_VRTX |
189 ENABLE_TRI_FAN_PROVOKE_VRTX |
190 LINE_STRIP_PROVOKE_VRTX(1) |
191 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D );
192 OUT_RING( _3DSTATE_MODES_4_CMD |
193 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
194 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
195 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff) );
196 OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2 );
197 OUT_RING( 0x00000000 ); /* Disable texture coordinate wrap-shortest */
198 OUT_RING( (1 << S4_POINT_WIDTH_SHIFT) |
199 S4_LINE_WIDTH_ONE |
200 S4_CULLMODE_NONE |
201 S4_VFMT_XY );
202 OUT_RING( 0x00000000 ); /* Stencil. */
203 OUT_RING( _3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT );
204 OUT_RING( _3DSTATE_SCISSOR_RECT_0_CMD );
205 OUT_RING( 0 );
206 OUT_RING( 0 );
207 OUT_RING( _3DSTATE_DEPTH_SUBRECT_DISABLE );
208 OUT_RING( _3DSTATE_LOAD_INDIRECT | 0 ); /* disable indirect state */
209 OUT_RING( 0 );
210 OUT_RING( _3DSTATE_STIPPLE );
211 OUT_RING( 0x00000000 );
212 OUT_RING( _3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
214 /* samler state */
215 #define TEX_COUNT 1
216 OUT_RING( _3DSTATE_MAP_STATE | (3 * TEX_COUNT) );
217 OUT_RING( (1 << TEX_COUNT) - 1 );
219 // Source buffer
220 OUT_RING( bm_src->framebuffer );
221 OUT_RING( src_format |
222 (bm_src->height - 1) << MS3_HEIGHT_SHIFT |
223 (bm_src->pitch/bm_src->bpp - 1) << MS3_WIDTH_SHIFT );
224 OUT_RING( (bm_src->pitch/4 -1) << MS4_PITCH_SHIFT );
226 OUT_RING( _3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT) );
227 OUT_RING( (1 << TEX_COUNT) - 1 );
228 OUT_RING( MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
229 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
230 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT );
231 OUT_RING( TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
232 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
233 0 << SS3_TEXTUREMAP_INDEX_SHIFT );
234 OUT_RING( 0x00000000 );
236 /* render target state */
238 // Destination buffer
239 OUT_RING( _3DSTATE_BUF_INFO_CMD );
240 OUT_RING( BUF_3D_ID_COLOR_BACK | bm_dst->pitch );
241 OUT_RING( bm_dst->framebuffer );
242 OUT_RING( _3DSTATE_DST_BUF_VARS_CMD );
243 OUT_RING( dst_format |
244 DSTORG_HORT_BIAS(0x8) |
245 DSTORG_VERT_BIAS(0x8) );
247 /* draw rect is unconditional */
248 OUT_RING( _3DSTATE_DRAW_RECT_CMD );
250 OUT_RING( 0x00000000 );
251 OUT_RING( 0x00000000 ); // ymin, xmin
252 OUT_RING( DRAW_YMAX(dst_y + dst_height - 1) |
253 DRAW_XMAX(dst_x + dst_width - 1) );
255 /* yorig, xorig (relate to color buffer?) */
256 OUT_RING( 0x00000000 );
258 /* texfmt */
259 OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2 );
260 OUT_RING( (4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT) );
261 OUT_RING( ~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
262 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) );
263 OUT_RING( S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
264 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
265 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
266 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT );
268 /* pixel shader */
269 OUT_RING( _3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2) );
270 /* decl FS_T0 */
271 OUT_RING( D0_DCL |
272 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
273 REG_NR(FS_T0) << D0_NR_SHIFT |
274 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
275 OUT_RING( 0 );
276 OUT_RING( 0 );
277 /* decl FS_S0 */
278 OUT_RING( D0_DCL |
279 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
280 (REG_NR(FS_S0) << D0_NR_SHIFT) |
281 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
282 OUT_RING( 0 );
283 OUT_RING( 0 );
284 /* texld(FS_OC, FS_S0, FS_T0 */
285 OUT_RING( T0_TEXLD |
286 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
287 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
288 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT) );
289 OUT_RING( (REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
290 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT) );
291 OUT_RING( 0 );
293 // rectangle
294 // 3--x
295 // | |
296 // 2--1
297 OUT_RING( PRIM3D_RECTLIST | (3*4 - 1) );
298 OUT_RING( pack_float( dst_x + dst_width) );
299 OUT_RING( pack_float( dst_y + dst_height) );
300 OUT_RING( pack_float(src_x + src_width) );
301 OUT_RING( pack_float(src_y + src_height) );
303 OUT_RING( pack_float( dst_x + 0 ) );
304 OUT_RING( pack_float( dst_y +dst_height) );
305 OUT_RING( pack_float(src_x + 0) );
306 OUT_RING( pack_float(src_y + src_height) );
308 OUT_RING( pack_float( dst_x + 0 ) );
309 OUT_RING( pack_float( dst_y + 0 ) );
310 OUT_RING( pack_float(src_x + 0) );
311 OUT_RING( pack_float(src_y + 0) );
313 ADVANCE_RING();
314 DO_FLUSH();
315 UNLOCK_HW
317 return TRUE;