revert between 56095 -> 55830 in arch
[AROS.git] / rom / usb / pciusbhc / uhci / uhcichip.h
blobe490fc33716bdea43934290f40868d707659b2ee
1 #ifndef UHCICHIP_H
2 #define UHCICHIP_H
4 /*
5 *----------------------------------------------------------------------------
6 * Includes for UHCI USB Controller
7 *----------------------------------------------------------------------------
8 * By Chris Hodges <chrisly@platon42.de>
9 */
11 #include <exec/types.h>
12 #include "hccommon.h"
14 /* PCI Class: PCI_CLASS_SERIAL_USB */
16 /* Framelist stuff
18 1. Standard approach
19 - Framelist contains all the same entries pointing to ISO-TD
20 - ISO-TD: is inactive by default. Links to Control-QH
21 - Control-QH: - Head links to Int-Queue
22 - Element: Links to dummy-TD if empty (inactive)
23 - Element: otherwise links to QH for control transfer
24 - Int-Queue : - Head links to Bulk-Queue
25 2. Not quite conform but better approach:
26 - Framelist contains pointers to the correct interrupt queue head,
27 depending on the interval (9 different QHs). The last 1ms qh points to the iso-td
28 - the iso-td points to the first Control-QH
29 - the control qh has vertical TDs for each transfer, and points to the next control qh
30 - the last control qh points to bulk qh.
31 - the bulk qh has vertical TDs for each (partial) transfer, and points to the next bulk qh
32 - the last bulk qh points to the terminating qh with terminating bits set.
36 * --------------------- UHCI registers ------------------------
37 * Warning: These are BYTE offsets!
40 #define UHCI_USBCMD 0x000 /* USB Command (r/w) */
41 #define UHCI_USBSTATUS 0x002 /* USB Status (r/wc) */
42 #define UHCI_USBINTEN 0x004 /* USB Interrupt Enable (r/w) */
43 #define UHCI_FRAMECOUNT 0x006 /* Frame Number (r/w) */
44 #define UHCI_FRAMELISTADDR 0x008 /* Framelist Base Address (LONGWORD!), 4KB aligned! (r/w) */
45 #define UHCI_SOFMOD 0x00c /* Start Of Frame Modify (upper byte?) (r/w) */
46 #define UHCI_PORT1STSCTRL 0x010 /* Port 1 Status/Control (r/wc) */
47 #define UHCI_PORT2STSCTRL 0x012 /* Port 2 Status/Control (r/wc) */
48 #define UHCI_USBLEGSUP 0x0c0 /* legacy support */
50 struct UHCIRegs
52 volatile UWORD uhr_USBCmd; /* USB Command (r/w) */
53 volatile UWORD uhr_USBStatus; /* USB Status (r/wc) */
54 volatile UWORD uhr_USBIntEn; /* USB Interrupt Enable (r/w) */
55 volatile UWORD uhr_FrameCount; /* Frame Number (r/w) */
56 volatile APTR uhr_FrameListAddr; /* Framelist Base Address (LONGWORD!) (r/w) */
57 volatile UBYTE uhr_SOFMod; /* Start Of Frame Modify (upper byte?) (r/w) */
58 volatile UBYTE uhr_Reserved0;
59 volatile UWORD uhr_Reserved1;
60 volatile UWORD uhr_PortStsCtrl[2]; /* Port 1/2 Status/Control (r/wc) */
63 /* UHCI_USBCMD defines */
64 #define UHCB_RUNSTOP 0 /* 1=Run, 0=Stop */
65 #define UHCB_HCRESET 1 /* Host Controller Reset */
66 #define UHCB_GLOBALRESET 2 /* Reset everything */
67 #define UHCB_USBSUSPEND 3 /* Send USB Suspend */
68 #define UHCB_USBRESUME 4 /* Send USB Resume */
69 #define UHCB_DEBUG 5 /* Software Debug */
70 #define UHCB_CONFIGURE 6 /* Semaphore */
71 #define UHCB_MAXPACKET64 7 /* 1=64 bytes, 0=32 bytes */
73 #define UHCF_RUNSTOP (1UL<<UHCB_RUNSTOP)
74 #define UHCF_HCRESET (1UL<<UHCB_HCRESET)
75 #define UHCF_GLOBALRESET (1UL<<UHCB_GLOBALRESET)
76 #define UHCF_USBSUSPEND (1UL<<UHCB_USBSUSPEND)
77 #define UHCF_USBRESUME (1UL<<UHCB_USBRESUME)
78 #define UHCF_DEBUG (1UL<<UHCB_DEBUG)
79 #define UHCF_CONFIGURE (1UL<<UHCB_CONFIGURE)
80 #define UHCF_MAXPACKET64 (1UL<<UHCB_MAXPACKET64)
82 /* UHCI_USBSTATUS defines */
83 #define UHSB_USBINT 0 /* TD completed */
84 #define UHSB_USBERRORINT 1 /* TD resulted in an error condition */
85 #define UHSB_RESUMEDTX 2 /* Resume detected */
86 #define UHSB_HCSYSERROR 3 /* HC PCI error */
87 #define UHSB_HCPROCERROR 4 /* HC has found a TD error */
88 #define UHSB_HCHALTED 5 /* HC has stopped execution */
90 #define UHSF_USBINT (1UL<<UHSB_USBINT)
91 #define UHSF_USBERRORINT (1UL<<UHSB_USBERRORINT)
92 #define UHSF_RESUMEDTX (1UL<<UHSB_RESUMEDTX)
93 #define UHSF_HCSYSERROR (1UL<<UHSB_HCSYSERROR)
94 #define UHSF_HCPROCERROR (1UL<<UHSB_HCPROCERROR)
95 #define UHSF_HCHALTED (1UL<<UHSB_HCHALTED)
97 /* UHCI_USBINTEN defines */
98 #define UHIB_TIMEOUTCRC 0 /* Timeout or CRC Interrupt Enable */
99 #define UHIB_RESUME 1 /* Resume Interrupt Enable */
100 #define UHIB_INTONCOMPLETE 2 /* Interrupt on Complete (IOC) Enable */
101 #define UHIB_SHORTPACKET 3 /* Short Packet Interrupt Enable */
103 #define UHIF_TIMEOUTCRC (1UL<<UHIB_TIMEOUTCRC)
104 #define UHIF_RESUME (1UL<<UHIB_RESUME)
105 #define UHIF_INTONCOMPLETE (1UL<<UHIB_INTONCOMPLETE)
106 #define UHIF_SHORTPACKET (1UL<<UHIB_SHORTPACKET)
108 /* UHCI_PORTxSTSCTRL defines */
109 #define UHPB_PORTCONNECTED 0 /* Port Connection status */
110 #define UHPB_CONNECTCHANGE 1 /* Port Connection change */
111 #define UHPB_PORTENABLE 2 /* Enable Port */
112 #define UHPB_ENABLECHANGE 3 /* Port Enable/Disable change */
113 #define UHPB_STATUSDPLUS 4 /* Status of D+ line */
114 #define UHPB_STATUSDMINUS 5 /* Status of D- line */
115 #define UHPB_RESUMEDTX 6 /* Resume detected */
116 #define UHPB_LOWSPEED 8 /* Low speed device connected */
117 #define UHPB_PORTRESET 9 /* Port is in reset state */
118 #define UHPB_PORTSUSPEND 12 /* Suspend Mode */
120 #define UHPF_PORTCONNECTED (1UL<<UHPB_PORTCONNECTED)
121 #define UHPF_CONNECTCHANGE (1UL<<UHPB_CONNECTCHANGE)
122 #define UHPF_PORTENABLE (1UL<<UHPB_PORTENABLE)
123 #define UHPF_ENABLECHANGE (1UL<<UHPB_ENABLECHANGE)
124 #define UHPF_STATUSDPLUS (1UL<<UHPB_STATUSDPLUS)
125 #define UHPF_STATUSDMINUS (1UL<<UHPB_STATUSDMINUS)
126 #define UHPF_RESUMEDTX (1UL<<UHPB_RESUMEDTX)
127 #define UHPF_LOWSPEED (1UL<<UHPB_LOWSPEED)
128 #define UHPF_PORTRESET (1UL<<UHPB_PORTRESET)
129 #define UHPF_PORTSUSPEND (1UL<<UHPB_PORTSUSPEND)
131 /* data structures */
133 #define UHCI_FRAMELIST_SIZE 1024
134 #define UHCI_FRAMELIST_ALIGNMENT 0x0fff
136 #define UHCI_TDQH_ALIGNMENT 0x0007
138 #define UHCI_QH_POOLSIZE 128
139 #define UHCI_TD_POOLSIZE 1024
141 #define UHCI_TD_CTRL_LIMIT 512 // limit for one batch of CTRL data TDs
142 #define UHCI_TD_INT_LIMIT 128 // limit for one batch of INT data TDs
143 #define UHCI_TD_BULK_LIMIT 32768 // limit for one batch of BULK data TDs
145 struct UhciXX
147 struct UhciXX *uxx_Succ;
148 struct UhciXX *uxx_Pred;
149 ULONG uxx_Self; /* LE PHYSICAL pointer to self + UHCI_TDSELECT */
150 APTR uxx_Private;
151 /* aligned to 16 bytes */
152 ULONG uxx_Link; /* LE PHYSICAL link pointer */
155 struct UhciTD
157 struct UhciXX *utd_Succ;
158 ULONG utd_Unused0;
159 //struct UhciXX *utd_Pred;
160 ULONG utd_Self; /* LE PHYSICAL pointer to self + UHCI_TDSELECT */
161 //struct UhciQH *utd_QueueHead; /* Pointer to queue head this thing belongs to (only for Ctrl/Bulk) */
162 ULONG utd_Unused1;
163 /* aligned to 16 bytes */
164 ULONG utd_Link; /* LE PHYSICAL TD Link Pointer (+BFS/DFS+QH/TD+TERM) */
165 ULONG utd_CtrlStatus; /* LE Control and Status word */
166 ULONG utd_Token; /* LE Token (Transfer length) */
167 ULONG utd_BufferPtr; /* LE PHYSICAL Data Buffer */
170 struct UhciQH
172 struct UhciXX *uqh_Succ;
173 struct UhciXX *uqh_Pred;
174 ULONG uqh_Self; /* LE PHYSICAL pointer to self + UHCI_QHSELECT */
175 struct IOUsbHWReq *uqh_IOReq; /* IO Request this belongs to */
176 /* aligned to 16 bytes */
177 ULONG uqh_Link; /* LE PHYSICAL QH Link Pointer (QH/TD+TERM) */
178 ULONG uqh_Element; /* LE PHYSICAL Queue Element Link Pointer (QH/TD+TERM) */
179 struct UhciTD *uqh_FirstTD; /* First TD */
180 ULONG uqh_Actual; /* Number of bytes for successful completion in this QH */
181 //struct UhciTD *uqh_LastTD; /* Last TD */
184 /* pointer defines */
186 #define UHCI_PTRMASK 0xfffffff0 /* frame list pointer mask */
187 #define UHCI_QHSELECT 0x00000002 /* pointer is a queue head */
188 #define UHCI_TDSELECT 0x00000000 /* pointer is a transfer descriptor */
189 #define UHCI_TERMINATE 0x00000001 /* terminate list here */
190 #define UHCI_DFS 0x00000004 /* depth first search (TD only) */
191 #define UHCI_BFS 0x00000000 /* breadth first search (TD only) */
193 /* TD control and status word defines */
195 #define UTSS_ACTUALLENGTH 0 /* actual length of data transferred */
196 #define UTSB_BITSTUFFERR 17 /* Bit-Stuffing error */
197 #define UTSB_CRCTIMEOUT 18 /* IN CRC error, OUT Timeout error */
198 #define UTSB_NAK 19 /* NAK received */
199 #define UTSB_BABBLE 20 /* Babble detected on the bus */
200 #define UTSB_DATABUFFERERR 21 /* Data Buffer Error */
201 #define UTSB_STALLED 22 /* TD stalled due to errors */
202 #define UTCB_ACTIVE 23 /* TD is active / enable TD */
203 #define UTCB_READYINTEN 24 /* enable interrupt on complete */
204 #define UTCB_ISOCHRONOUS 25 /* enable isochronous transfer */
205 #define UTCB_LOWSPEED 26 /* device is lowspeed */
206 #define UTCS_ERRORLIMIT 27 /* how many errors permitted */
207 #define UTCB_SHORTPACKET 29 /* enable short packet detection */
209 #define UTSM_ACTUALLENGTH (((1UL<<11)-1)<<UTSS_ACTUALLENGTH)
210 #define UTSF_BITSTUFFERR (1UL<<UTSB_BITSTUFFERR)
211 #define UTSF_CRCTIMEOUT (1UL<<UTSB_CRCTIMEOUT)
212 #define UTSF_NAK (1UL<<UTSB_NAK)
213 #define UTSF_BABBLE (1UL<<UTSB_BABBLE)
214 #define UTSF_DATABUFFERERR (1UL<<UTSB_DATABUFFERERR)
215 #define UTSF_STALLED (1UL<<UTSB_STALLED)
216 #define UTCF_ACTIVE (1UL<<UTCB_ACTIVE)
217 #define UTCF_READYINTEN (1UL<<UTCB_READYINTEN)
218 #define UTCF_ISOCHRONOUS (1UL<<UTCB_ISOCHRONOUS)
219 #define UTCF_LOWSPEED (1UL<<UTCB_LOWSPEED)
220 #define UTCF_SHORTPACKET (1UL<<UTCB_SHORTPACKET)
222 #define UTCM_ERRORLIMIT (((1UL<<2)-1)<<UTCS_ERRORLIMIT)
223 #define UTCF_NOERRORLIMIT (0UL<<UTCS_ERRORLIMIT)
224 #define UTCF_1ERRORLIMIT (1UL<<UTCS_ERRORLIMIT)
225 #define UTCF_2ERRORSLIMIT (2UL<<UTCS_ERRORLIMIT)
226 #define UTCF_3ERRORSLIMIT (3UL<<UTCS_ERRORLIMIT)
228 /* TD Token word defines */
230 #define UTTS_PID 0 /* Packet ID */
231 #define UTTS_DEVADDR 8 /* Device address */
232 #define UTTS_ENDPOINT 15 /* Endpoint address */
233 #define UTTB_DATA1 19 /* DATA1 toggle */
234 #define UTTS_TRANSLENGTH 21 /* (maximum) length of the transfer */
236 #define UTTF_DATA0 (0UL<<UTTB_DATA1)
237 #define UTTF_DATA1 (1UL<<UTTB_DATA1)
239 #define UTTM_PID (((1UL<<8)-1)<<UTTS_PID)
240 #define UTTM_DEVADDR (((1UL<<7)-1)<<UTTS_DEVADDR)
241 #define UTTM_ENDPOINT (((1UL<<4)-1)<<UTTS_ENDPOINT)
242 #define UTTM_TRANSLENGTH (((1UL<<11)-1)<<UTTS_TRANSLENGTH)
244 #endif /* UHCICHIP_H */