rom/hidds/pci/pcie.h

   1 #ifndef _PCIE_H
   2 #define _PCIE_H
   3
   4 /*
   5     Copyright © 2014, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 /*
  10     PCI Express Configspace offsets
  11 */
  12 #define PCIECS_VENDOR        0x00
  13 #define PCIECS_PRODUCT       0x02
  14 #define PCIECS_COMMAND       0x04
  15 #define PCIECS_STATUS        0x06
  16 #define PCIECS_REVISION      0x08
  17 #define PCIECS_PROGIF        0x09
  18 #define PCIECS_SUBCLASS      0x0a
  19 #define PCIECS_CLASS         0x0b
  20 #define PCIECS_CACHELS       0x0c
  21 #define PCIECS_LATENCY       0x0d
  22 #define PCIECS_HEADERTYPE    0x0e
  23 #define PCIECS_BIST          0x0f
  24 #define PCIECS_BAR0          0x10
  25 #define PCIECS_BAR1          0x14
  26 #define PCIECS_BAR2          0x18
  27 #define PCIECS_BAR3          0x1c
  28 #define PCIECS_BAR4          0x20
  29 #define PCIECS_BAR5          0x24
  30 #define PCIECS_CARDBUS_CIS   0x28
  31 #define PCIECS_SUBVENDOR     0x2c
  32 #define PCIECS_SUBSYSTEM     0x2e
  33 #define PCIECS_EXPROM_BASE   0x30
  34 #define PCIECS_CAP_PTR       0x34
  35 #define PCIECS_INT_LINE      0x3c
  36 #define PCIECS_INT_PIN       0x3d
  37 #define PCIECS_MIN_GNT       0x3e
  38 #define PCIECS_MAX_LAT       0x3f
  39
  40 /*
  41     PCI Express capability structure, rev. 3.0
  42 */
  43 #define PCIECS_CAPID        0x00
  44 #define PCIECS_NEXTCAP      0x01
  45 #define PCIECS_PCIECAP      0x02
  46 #define PCIECS_DEVCAP       0x04
  47 #define PCIECS_DEVCTL       0x08
  48 #define PCIECS_DEVSTS       0x0A
  49 #define PCIECS_LINKCAP      0x0C
  50 #define PCIECS_LINKCTL      0x10
  51 #define PCIECS_LINKSTS      0x12
  52 #define PCIECS_SLOTCAP      0x14
  53 #define PCIECS_SLOTCTL      0x18
  54 #define PCIECS_SLOTSTS      0x1A
  55 #define PCIECS_ROOTCTL      0x1C
  56 #define PCIECS_ROOTSTS      0x20    /* rev 1.0 */
  57 #define PCIECS_DEVCAP2      0x24
  58 #define PCIECS_DEVCTL2      0x28
  59 #define PCIECS_DEVSTS2      0x2A
  60 #define PCIECS_LINKCAP2     0x2C
  61 #define PCIECS_LINKCTL2     0x30
  62 #define PCIECS_LINKSTS2     0x32
  63 #define PCIECS_SLOTCAP2     0x34
  64 #define PCIECS_SLOTCTL2     0x38
  65 #define PCIECS_SLOTSTS2     0x3A    /* rev 3.0 */
  66
  67 /*
  68     PCI Express capabilities, PCIECS_PCIECAP (incomplete)
  69 */
  70 #define PCIECAP_VER_MASK    0x0F
  71 #define PCIECAP_VER_10      0x01     /* PCIe spec 1.0 */
  72 #define PCIECAP_VER_20      0x02     /* PCIe spec 2.0 */
  73
  74 /*
  75     PCI Express extended capabilities
  76 */
  77 #define PCIEECAP_AER        0x0001  /* Advanced Error Handling */
  78 #define PCIEECAP_VC         0x0002  /* Virtual Channel */
  79 #define PCIEECAP_SER        0x0003  /* Serial Number */
  80 #define PCIEECAP_PWR_BUDGET 0x0004  /* Power Budgeting */
  81
  82 #endif /* _PCIE_H */
  83