| blob | 591439ecc4da66698c98a13537099bb078018e0c |
1 #ifndef XHCICHIP_H
2 #define XHCICHIP_H
4 /*
5 *----------------------------------------------------------------------------
6 * Includes for XHCI USB Controller
7 *----------------------------------------------------------------------------
8 */
10 /*
11 XHCI_xxx's are offsets to something
12 XHCB_xxx's are bitnumbers
13 XHCF_xxx's are flags
14 XHCM_xxx's are bitmasks
15 XHCV_xxx(p)'s return shifted values from p
16 */
18 #define opreg_readl(opreg) READREG32_LE(hc->xhc_opregbase, opreg)
19 #define opreg_writel(opreg, value) WRITEREG32_LE(hc->xhc_opregbase, opreg, value)
21 #define capreg_readl(capreg) READREG32_LE(hc->xhc_capregbase, capreg)
22 #define capreg_readw(capreg) READREG16_LE(hc->xhc_capregbase, capreg)
23 #define capreg_readb(capreg) (*((volatile UBYTE *) (((UBYTE *) (hc->xhc_capregbase)) + ((ULONG) (capreg)))))
26 /* XHCI capability register defines */
27 #define XHCI_CAPLENGTH 0x00
28 #define XHCI_HCIVERSION 0x02
29 #define XHCI_HCSPARAMS1 0x04
30 #define XHCI_HCSPARAMS2 0x08
31 #define XHCI_HCSPARAMS3 0x0C
32 #define XHCI_HCCPARAMS 0x10
33 #define XHCI_DBOFF 0x14
34 #define XHCI_RTSOFF 0x18
37 /* XHCI_HCSPARAMS1 defines */
38 #define XHCB_MaxSlots 0
39 #define XHCB_MaxIntrs 8
40 #define XHCB_MaxPorts 24
42 #define XHCM_MaxSlots (((1UL<<8)-1)<<XHCB_MaxSlots)
43 #define XHCM_MaxIntrs (((1UL<<11)-1)<<XHCB_MaxIntrs)
44 #define XHCM_MaxPorts (((1UL<<8)-1)<<XHCB_MaxPorts)
46 #define XHCV_MaxPorts(p) (((p)&XHCM_MaxPorts)>>XHCB_MaxPorts)
47 #define XHCV_MaxIntrs(p) (((p)&XHCM_MaxIntrs)>>XHCB_MaxIntrs)
48 #define XHCV_MaxSlots(p) (((p)&XHCM_MaxSlots)>>XHCB_MaxSlots)
51 /* XHCI_HCSPARAMS2 defines */
52 #define XHCB_IST 0
53 #define XHCB_ERST_Max 4
54 #define XHCB_SPR 26
55 #define XHCB_SPB_Max 27
57 #define XHCM_IST (((1UL<<4)-1)<<XHCB_IST)
58 #define XHCM_ERST_Max ((1UL<<4)-1)<<XHCB_ERST_Max)
59 #define XHCF_SPR (1UL<<XHCB_SPR)
60 #define XHCM_SPB_Max (((1UL<<4)-1)<<XHCB_SPB_Max)
61 #define XHCV_SPB_Max(p) (((p)&XHCM_SPB_Max)>>XHCB_SPB_Max)
63 /* XHCI_HCSPARAMS3 defines */
64 #define XHCB_U1DEV_LAT 0
65 #define XHCB_U2DEV_LAT 16
67 #define XHCM_U1DEV_LAT (((1UL<<8)-1)<<XHCB_U1DEV_LAT)
68 #define XHCM_U2DEV_LAT (((1UL<<16)-1)<<XHCB_U2DEV_LAT)
71 /* XHCI_HCCPARAMS defines */
72 #define XHCB_AC64 0
73 #define XHCB_BNC 1
74 #define XHCB_CSZ 2
75 #define XHCB_PPC 3
76 #define XHCB_PIND 4
77 #define XHCB_LHRC 5
78 #define XHCB_LTC 6
79 #define XHCB_NSS 7
80 #define XHCB_MaxPSASize 12
81 #define XHCB_xECP 16
83 #define XHCF_AC64 (1UL<<XHCB_AC64)
84 #define XHCF_BNC (1UL<<XHCB_BNC)
85 #define XHCF_CSZ (1UL<<XHCB_CSZ)
86 #define XHCF_PPC (1UL<<XHCB_PPC)
87 #define XHCF_PIND (1UL<<XHCB_PIND)
88 #define XHCF_LHRC (1UL<<XHCB_LHRC)
89 #define XHCF_LTC (1UL<<XHCB_LTC)
90 #define XHCF_NSS (1UL<<XHCB_NSS)
91 #define XHCM_MaxPSASize (((1UL<<4)-1)<<XHCB_MaxPSASize)
92 #define XHCM_xECP (((1UL<<16)-1)<<XHCB_xECP)
93 #define XHCV_xECP(p) ((((p)&XHCM_xECP)>>XHCB_xECP)<<2)
96 /* Extended capability IDs */
97 #define XHCB_EXT_CAPS_ID 0
98 #define XHCB_EXT_CAPS_NEXT 8
99 #define XHCB_EXT_CAPS_VALUE 16
101 #define XHCM_EXT_CAPS_ID (((1UL<<8)-1)<<XHCB_EXT_CAPS_ID)
102 #define XHCM_EXT_CAPS_NEXT (((1UL<<8)-1)<<XHCB_EXT_CAPS_NEXT)
103 #define XHCM_EXT_CAPS_VALUE (((1UL<<16)-1)<<XHCB_EXT_CAPS_VALUE)
105 #define XHCV_EXT_CAPS_ID(p) (((p)&XHCM_EXT_CAPS_ID)>>XHCB_EXT_CAPS_ID)
106 #define XHCV_EXT_CAPS_NEXT(p) ((((p)&XHCM_EXT_CAPS_NEXT)>>XHCB_EXT_CAPS_NEXT)<<2)
107 #define XHCV_EXT_CAPS_VALUE(p) (((p)&XHCM_EXT_CAPS_VALUE)>>XHCB_EXT_CAPS_VALUE)
110 /* Reserved ID 0 */
111 #define XHCI_EXT_CAPS_LEGACY 1
112 #define XHCI_EXT_CAPS_PROTOCOL 2
113 #define XHCI_EXT_CAPS_XPOWERMNG 3
114 #define XHCI_EXT_CAPS_IOVIRT 4
115 #define XHCI_EXT_CAPS_MSGINTR 5
116 #define XHCI_EXT_CAPS_LOCALMEM 6
117 /* Reserved IDs 7-9 */
118 #define XHCI_EXT_CAPS_USBDEBUG 10
119 /* Reserved IDs 11-16 */
120 #define XHCI_EXT_CAPS_XMSGINTR 17
121 /* Reserved IDs 18-191 */
122 /* Vendor defined IDs 192-255 */
123 #define XHCI_EXT_CAPS_MAX 255
126 /* These are for XHCI_EXT_CAPS_LEGACY */
127 /* USB Legacy Support Capability (USBLEGSUP) */
128 #define XHCI_USBLEGSUP 0x00
129 #define XHCB_BIOSOWNED 16
130 #define XHCB_OSOWNED 24
131 #define XHCF_BIOSOWNED (1UL<<XHCB_BIOSOWNED)
132 #define XHCF_OSOWNED (1UL<<XHCB_OSOWNED)
134 /* USB Legacy Support Control/Status (USBLEGCTLSTS) */
135 #define XHCI_USBLEGCTLSTS 0x04
136 #define XHCB_SMI_USBE 0
137 #define XHCB_SMI_HSEE 4
138 #define XHCB_SMI_OSOE 13
139 #define XHCB_SMI_PCICE 14
140 #define XHCB_SMI_BARE 15
141 #define XHCB_SMI_EI 16
142 #define XHCB_SMI_HSE 20
143 #define XHCB_SMI_OSOC 29
144 #define XHCB_SMI_PCIC 30
145 #define XHCB_SMI_BAR 31
147 #define XHCF_SMI_USBE (1UL<<XHCB_SMI_USBE)
148 #define XHCF_SMI_HSEE (1UL<<XHCB_SMI_HSEE)
149 #define XHCF_SMI_OSOE (1UL<<XHCB_SMI_OSOE)
150 #define XHCF_SMI_PCICE (1UL<<XHCB_SMI_PCICE)
151 #define XHCF_SMI_BARE (1UL<<XHCB_SMI_BARE)
152 #define XHCF_SMI_EI (1UL<<XHCB_SMI_EI)
153 #define XHCF_SMI_HSE (1UL<<XHCB_SMI_HSE)
154 #define XHCF_SMI_OSOC (1UL<<XHCB_SMI_OSOC)
155 #define XHCF_SMI_PCIC (1UL<<XHCB_SMI_PCIC)
156 #define XHCF_SMI_BAR (1UL<<XHCB_SMI_BAR)
159 /* XHCI operational register defines */
160 /* USB Command Register (USBCMD) */
161 #define XHCI_USBCMD 0x00
163 #define XHCB_CMD_RS 0
164 #define XHCB_CMD_HCRST 1
165 #define XHCB_CMD_INTE 2
166 #define XHCB_CMD_HSEE 3
167 #define XHCB_CMD_LHCRST 7
168 #define XHCB_CMD_CSS 8
169 #define XHCB_CMD_CRS 9
170 #define XHCB_CMD_EWE 10
171 #define XHCB_CMD_EU3S 11
173 #define XHCF_CMD_RS (1UL<<XHCB_CMD_RS)
174 #define XHCF_CMD_HCRST (1UL<<XHCB_CMD_HCRST)
175 #define XHCF_CMD_INTE (1UL<<XHCB_CMD_INTE)
176 #define XHCF_CMD_HSEE (1UL<<XHCB_CMD_HSEE)
177 #define XHCF_CMD_LHCRST (1UL<<XHCB_CMD_LHCRST)
178 #define XHCF_CMD_CSS (1UL<<XHCB_CMD_CSS)
179 #define XHCF_CMD_CRS (1UL<<XHCB_CMD_CRS)
180 #define XHCF_CMD_EWE (1UL<<XHCB_CMD_EWE)
181 #define XHCF_CMD_EU3S (1UL<<XHCB_CMD_EU3S)
183 /* USB Status Register (USBSTS) */
184 #define XHCI_USBSTS 0x04
185 #define XHCB_STS_HCH 0
186 #define XHCB_STS_HSE 2
187 #define XHCB_STS_EINT 3
188 #define XHCB_STS_PCD 4
189 #define XHCB_STS_SSS 8
190 #define XHCB_STS_RSS 9
191 #define XHCB_STS_SRE 10
192 #define XHCB_STS_CNR 11
193 #define XHCB_STS_HCE 12
195 #define XHCF_STS_HCH (1UL<<XHCB_STS_HCH)
196 #define XHCF_STS_HSE (1UL<<XHCB_STS_HSE)
197 #define XHCF_STS_EINT (1UL<<XHCB_STS_EINT)
198 #define XHCF_STS_PCD (1UL<<XHCB_STS_PCD)
199 #define XHCF_STS_SSS (1UL<<XHCB_STS_SSS)
200 #define XHCF_STS_RSS (1UL<<XHCB_STS_RSS)
201 #define XHCF_STS_SRE (1UL<<XHCB_STS_SRE)
202 #define XHCF_STS_CNR (1UL<<XHCB_STS_CNR)
203 #define XHCF_STS_HCE (1UL<<XHCB_STS_HCE)
205 /* Page Size Register (PAGESIZE) */
206 #define XHCI_PAGESIZE 0x08
208 /* Device Notification Control Register (DNCTRL) */
209 #define XHCI_DNCTRL 0x14
211 /* Command Ring Control Register (CRCR) */
212 #define XHCI_CRCR 0x18
214 /* Device Context Base Address Array Pointer Register (DCBAAP) */
215 #define XHCI_DCBAAP 0x30
217 /* Configure Register (CONFIG) */
218 #define XHCI_CONFIG 0x38
219 #define XHCB_CONFIG_MaxSlotsEn 0
220 #define XHCM_CONFIG_MaxSlotsEn (((1UL<<8)-1)<<XHCB_CONFIG_MaxSlotsEn)
222 /* Port Status and Control Register (PORTSC) */
223 #define XHCI_PORTSC(port) (0x400 + (0x10 * (port-1)))
225 #define XHCB_PS_CCS 0
226 #define XHCB_PS_PED 1
227 #define XHCB_PS_OCA 3
228 #define XHCB_PS_PR 4
229 #define XHCB_PS_PLS 5
230 #define XHCB_PS_PP 9
231 #define XHCB_PS_SPEED 10
232 #define XHCB_PS_PIC 14
233 #define XHCB_PS_LWS 16
234 #define XHCB_PS_CSC 17
235 #define XHCB_PS_PEC 18
236 #define XHCB_PS_WRC 19
237 #define XHCB_PS_OCC 20
238 #define XHCB_PS_PRC 21
239 #define XHCB_PS_PLC 22
240 #define XHCB_PS_CEC 23
241 #define XHCB_PS_CAS 24
242 #define XHCB_PS_WCE 25
243 #define XHCB_PS_WDE 26
244 #define XHCB_PS_WOE 27
245 #define XHCB_PS_DR 30
246 #define XHCB_PS_WPR 31
248 #define XHCF_PS_CCS (1UL<<XHCB_PS_CCS)
249 #define XHCF_PS_PED (1UL<<XHCB_PS_PED)
250 #define XHCF_PS_OCA (1UL<<XHCB_PS_OCA)
251 #define XHCF_PS_PR (1UL<<XHCB_PS_PR)
252 #define XHCM_PS_PLS (((1UL<<4)-1)<<XHCB_PS_PLS)
253 #define XHCF_PS_PP (1UL<<XHCB_PS_PP)
254 #define XHCM_PS_SPEED (((1UL<<4)-1)<<XHCB_PS_SPEED)
255 #define XHCM_PS_PIC (((1UL<<2)-1)<<XHCB_PS_PIC)
256 #define XHCF_PS_LWS (1UL<<XHCB_PS_LWS)
257 #define XHCF_PS_CSC (1UL<<XHCB_PS_CSC)
258 #define XHCF_PS_PEC (1UL<<XHCB_PS_PEC)
259 #define XHCF_PS_WRC (1UL<<XHCB_PS_WRC)
260 #define XHCF_PS_OCC (1UL<<XHCB_PS_OCC)
261 #define XHCF_PS_PRC (1UL<<XHCB_PS_PRC)
262 #define XHCF_PS_PLC (1UL<<XHCB_PS_PLC)
263 #define XHCF_PS_CEC (1UL<<XHCB_PS_CEC)
264 #define XHCF_PS_CAS (1UL<<XHCB_PS_CAS)
265 #define XHCF_PS_WCE (1UL<<XHCB_PS_WCE)
266 #define XHCF_PS_WDE (1UL<<XHCB_PS_WDE)
267 #define XHCF_PS_WOE (1UL<<XHCB_PS_WOE)
268 #define XHCF_PS_DR (1UL<<XHCB_PS_DR)
269 #define XHCF_PS_WPR (1UL<<XHCB_PS_WPR)