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includes: AROS_UFIxx -> AROS_INTxx change
[AROS.git] / workbench / devs / USB / drivers / UHCI / uhciclass.c
blobedcbeddbaa508694d2b41f2c188f25122d93fd24
1 /*
2 Copyright (C) 2006 by Michal Schulz
3 $Id$
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU Library General Public License as
7 published by the Free Software Foundation; either version 2 of the
8 License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU Library General Public
16 License along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #define DEBUG 0
22
23 #include <inttypes.h>
24
25 #include <aros/symbolsets.h>
26
27 #include <aros/debug.h>
28
29 #include <exec/types.h>
30 #include <exec/lists.h>
31 #include <exec/interrupts.h>
32 #include <exec/errors.h>
33 #include <oop/oop.h>
34
35 #include <hidd/hidd.h>
36 #include <hidd/pci.h>
37
38 #include <usb/usb.h>
39
40 #include <asm/io.h>
41
42 #include <proto/oop.h>
43 #include <proto/utility.h>
44
45 #include <dos/dos.h>
46
47 #include <string.h>
48 #include <stdio.h>
49
50 #include "uhci.h"
51
52 OOP_AttrBase HiddUHCIAttrBase;
53
54 static AROS_INTH1(HubInterrupt, UHCIData *, uhci)
55 {
56 AROS_INTFUNC_INIT
57
58 /* Signal the HUB process about incoming interrupt */
59 uint8_t sts = 0;
60 struct Interrupt *intr;
61
62 /* Remove itself from msg list */
63 GetMsg(&uhci->mport);
64
65 if (uhci->timereq->tr_node.io_Error == IOERR_ABORTED)
66 {
67 D(bug("[UHCI] INTR Aborted\n"));
68 return FALSE;
69 }
70
71 if (inw(uhci->iobase + UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
72 sts |= 1;
73 if (inw(uhci->iobase + UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
74 sts |= 2;
75
76 D(bug("[UHCI.%04x] Status on port: 1=%04x, 2=%04x\n", uhci->iobase, inw(uhci->iobase + UHCI_PORTSC1), inw(uhci->iobase + UHCI_PORTSC2)));
77
78 if (sts & 1)
79 (bug("[UHCI] Status change on port 1\n"));
80 if (sts & 2)
81 (bug("[UHCI] Status change on port 2\n"));
82
83 if (sts && uhci->running)
84 {
85 D(bug("Causing interrupts from list %p\n", &uhci->intList));
86 ForeachNode(&uhci->intList, intr)
87 {
88 Cause(intr);
89 }
90 }
91
92 uhci->timereq->tr_node.io_Command = TR_ADDREQUEST;
93 uhci->timereq->tr_time.tv_secs = 0;
94 uhci->timereq->tr_time.tv_micro = 255000;
95 SendIO((struct IORequest *)uhci->timereq);
96
97 return FALSE;
98
99 AROS_INTFUNC_EXIT
100 }
101
102 static AROS_INTH1(uhci_Handler, UHCIData *, uhci)
103 {
104 AROS_INTFUNC_INIT
105
106 UHCI_Pipe *p;
107
108 uint16_t status = inw(uhci->iobase + UHCI_STS);
109 uint16_t frame = inw(uhci->iobase + UHCI_FRNUM);
110 uint16_t port1 = inw(uhci->iobase + UHCI_PORTSC1);
111 uint16_t port2 = inw(uhci->iobase + UHCI_PORTSC2);
112 uint16_t cmd = inw(uhci->iobase + UHCI_CMD);
113 uint16_t sof = inb(uhci->iobase + UHCI_SOF);
114
115 (void)frame; //unused;
116 (void)port1; // unused
117 (void)port2; // unused
118 (void)sof; // unused;
119 (void)cmd; // unused;
120
121 /* Check if there's really an interrupt for us */
122 if((status & UHCI_STS_USBINT) == 0)
123 {
124 outw(status, uhci->iobase + UHCI_STS);
125 return FALSE;
126 }
127
128 D(bug("[UHCI] INTR Cmd=%04x, SOF=%04x, Status = %04x, Frame=%04x, PortSC1=%04x, PortSC2=%04x\n",
129 cmd, sof, status, frame, port1, port2));
130
131 if (!IsListEmpty(&uhci->Interrupts))
132 {
133 Disable();
134 ForeachNode(&uhci->Interrupts, p)
135 {
136 /* If the Linkptr of queue does not point to the first transfer descriptor, an interrupt
137 * has occured. Unfortunately, only the first one, who has added the interrupt to this
138 * pipe may receive data */
139 if ((p->p_Queue->qh_VLink & 0xfffffff1) != (uint32_t)p->p_FirstTD)
140 {
141 struct UHCI_Interrupt *intr;
142
143 if (!(p->p_FirstTD->td_Status & UHCI_TD_NAK))
144 {
145 D(bug("[UHCI] Interrupt!!! pipe %p, vlink=%p, FirstTD=%p\n", p, p->p_Queue->qh_VLink, p->p_FirstTD));
146 ForeachNode(&p->p_Intr, intr)
147 {
148 D(bug("[UHCI] Issuing interrupt %p\n", intr));
149 Cause(intr->i_intr);
150 }
151 }
152
153 /* Reactivate the transfer descriptor */
154 p->p_FirstTD->td_Status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3)
155 | UHCI_TD_ACTIVE
156 | UHCI_TD_IOC);
157
158 p->p_FirstTD->td_Token ^= 1 << 19;
159
160 if (p->p_FullSpeed)
161 p->p_FirstTD->td_Status |= UHCI_TD_SPD;
162 else
163 p->p_FirstTD->td_Status |= UHCI_TD_LS | UHCI_TD_SPD;
164
165 /* Link the first TD to the Queue header */
166 p->p_Queue->qh_VLink = (uint32_t)p->p_FirstTD | UHCI_PTR_TD;
167 }
168 }
169 Enable();
170 }
171
172 if (!IsListEmpty(&uhci->ControlLS))
173 {
174 Disable();
175 ForeachNode(&uhci->ControlLS, p)
176 {
177 UHCI_TransferDesc *td = (UHCI_TransferDesc *)p->p_FirstTD;
178 BOOL changed = FALSE;
179
180 if (p->p_Queue->qh_VLink == UHCI_PTR_T)
181 p->p_LastTD = (APTR)UHCI_PTR_T;
182
183 D(
184 UHCI_TransferDesc *t = (UHCI_TransferDesc *)(p->p_Queue->qh_VLink & 0xfffffff1);
185 bug("[UHCI] Control Low: p->p_Queue->qh_VLink=%p\n", p->p_Queue->qh_VLink);
186 while ((uint32_t)t != UHCI_PTR_T)
187 {
188 bug("[UHCI] TD=%p (%08x %08x %08x %08x)\n", t,
189 t->td_LinkPtr, t->td_Status, t->td_Token, t->td_Buffer);
190 t = (UHCI_TransferDesc *)(t->td_LinkPtr & 0xfffffff1);
191 }
192 );
193
194 while ((uint32_t)td != (p->p_Queue->qh_VLink & 0xfffffff1))
195 {
196 D(bug("[UHCI] TD=%p\n", td));
197 UHCI_TransferDesc *tnext = (UHCI_TransferDesc *)(td->td_LinkPtr & 0xfffffff1);
198 uhci_FreeTDQuick(uhci, td);
199 td = tnext;
200 p->p_FirstTD = tnext;
201 changed = TRUE;
202 }
203
204 if (changed && p->p_Queue->qh_VLink == UHCI_PTR_T) {
205 D(bug("[UHCI] INTR Control pipe %p empty (slow)\n", p));
206 p->p_ErrorCode = 0;
207
208 if (p->p_SigTask)
209 Signal(p->p_SigTask, 1 << p->p_Signal);
210 }
211 }
212 Enable();
213 }
214
215 if (!IsListEmpty(&uhci->ControlFS))
216 {
217 Disable();
218 ForeachNode(&uhci->ControlFS, p)
219 {
220 UHCI_TransferDesc *td = (UHCI_TransferDesc *)p->p_FirstTD;
221 BOOL changed = FALSE;
222
223 if (p->p_Queue->qh_VLink & UHCI_PTR_T)
224 p->p_LastTD = (APTR)UHCI_PTR_T;
225
226 D(
227 UHCI_TransferDesc *t = (UHCI_TransferDesc *)(p->p_Queue->qh_VLink & 0xfffffff1);
228 bug("[UHCI] Control Fast: p->p_Queue->qh_VLink=%p\n", p->p_Queue->qh_VLink);
229 while (!((uint32_t)t & UHCI_PTR_T))
230 {
231 bug("[UHCI] TD=%p (%08x %08x %08x %08x)\n", t,
232 t->td_LinkPtr, t->td_Status, t->td_Token, t->td_Buffer);
233 t = (UHCI_TransferDesc *)(t->td_LinkPtr & 0xfffffff1);
234 }
235 );
236
237
238 while ((uint32_t)td != (p->p_Queue->qh_VLink & 0xfffffff1))
239 {
240 D(bug("[UHCI] TD=%p\n", td));
241
242 UHCI_TransferDesc *tnext = (UHCI_TransferDesc *)(td->td_LinkPtr & 0xfffffff1);
243 uhci_FreeTDQuick(uhci, td);
244 td = tnext;
245 p->p_FirstTD = tnext;
246 changed = TRUE;
247 }
248
249 if (changed && p->p_Queue->qh_VLink == UHCI_PTR_T) {
250 D(bug("[UHCI] INTR Control pipe %p empty\n", p));
251 p->p_ErrorCode = 0;
252
253 if (p->p_SigTask)
254 Signal(p->p_SigTask, 1 << p->p_Signal);
255 }
256 /* Free the unused TD's */
257 }
258 Enable();
259 }
260
261 if (!IsListEmpty(&uhci->Bulk))
262 {
263 Disable();
264 ForeachNode(&uhci->Bulk, p)
265 {
266 UHCI_TransferDesc *td = (UHCI_TransferDesc *)p->p_FirstTD;
267 BOOL changed = FALSE;
268
269 if (p->p_Queue->qh_VLink == UHCI_PTR_T)
270 p->p_LastTD = (APTR)UHCI_PTR_T;
271
272 D(
273 UHCI_TransferDesc *t = (UHCI_TransferDesc *)(p->p_Queue->qh_VLink & 0xfffffff1);
274 bug("[UHCI] Bulk: p=%p, p->p_Queue->qh_VLink=%p\n", p, p->p_Queue->qh_VLink);
275 while ((uint32_t)t != UHCI_PTR_T)
276 {
277 bug("[UHCI] TD=%p (%08x %08x %08x %08x)\n", t,
278 t->td_LinkPtr, t->td_Status, t->td_Token, t->td_Buffer);
279 t = (UHCI_TransferDesc *)(t->td_LinkPtr & 0xfffffff1);
280 }
281 );
282
283 while ((uint32_t)td != (p->p_Queue->qh_VLink & 0xfffffff1))
284 {
285 UHCI_TransferDesc *tnext = (UHCI_TransferDesc *)(td->td_LinkPtr & 0xfffffff1);
286 uhci_FreeTDQuick(uhci, td);
287 td = tnext;
288 p->p_FirstTD = tnext;
289 changed = TRUE;
290 }
291
292 if (changed && p->p_Queue->qh_VLink == UHCI_PTR_T) {
293 D(bug("[UHCI] INTR Bulk pipe %p empty\n", p));
294 p->p_ErrorCode = 0;
295
296 if (p->p_SigTask)
297 Signal(p->p_SigTask, 1 << p->p_Signal);
298 }
299 }
300 Enable();
301 }
302
303 outw(status, uhci->iobase + UHCI_STS);
304
305 return FALSE;
306
307 AROS_INTFUNC_EXIT
308 }
309
310 OOP_Object *METHOD(UHCI, Root, New)
311 {
312 D(bug("[UHCI] UHCI::New()\n"));
313
314 BASE(cl->UserData)->LibNode.lib_OpenCnt++;
315
316 o = (OOP_Object *)OOP_DoSuperMethod(cl, o, (OOP_Msg) msg);
317 if (o)
318 {
319 int i;
320 UHCIData *uhci = OOP_INST_DATA(cl, o);
321
322 NEWLIST(&uhci->mport.mp_MsgList);
323 uhci->mport.mp_Flags = PA_SOFTINT;
324 uhci->mport.mp_Node.ln_Type = NT_MSGPORT;
325 uhci->mport.mp_SigTask = &uhci->timerint;
326 uhci->timerint.is_Code = (VOID_FUNC)HubInterrupt;
327 uhci->timerint.is_Data = uhci;
328
329 uhci->timereq = CreateIORequest(&uhci->mport, sizeof(struct timerequest));
330 OpenDevice((STRPTR)"timer.device", UNIT_VBLANK, (struct IORequest *)uhci->timereq, 0);
331
332 uhci->sd = SD(cl);
333
334 NEWLIST(&uhci->Isochronous);
335 NEWLIST(&uhci->Interrupts);
336 NEWLIST(&uhci->ControlLS);
337 NEWLIST(&uhci->ControlFS);
338 NEWLIST(&uhci->Bulk);
339
340 NEWLIST(&uhci->intList);
341
342 if (uhci->tmp)
343 AddTail(&uhci->intList, (struct Node *)uhci->tmp);
344
345 uhci->tr = (struct timerequest *)CreateIORequest(
346 CreateMsgPort(), sizeof(struct timerequest));
347
348 FreeSignal(uhci->tr->tr_node.io_Message.mn_ReplyPort->mp_SigBit);
349 uhci->tr->tr_node.io_Message.mn_ReplyPort->mp_SigBit = SIGBREAKB_CTRL_D;
350 OpenDevice((STRPTR)"timer.device", UNIT_MICROHZ, (struct IORequest *)uhci->tr, 0);
351
352 uhci->iobase = GetTagData(aHidd_UHCI_IOBase, 0, msg->attrList);
353 uhci->device = (OOP_Object *)GetTagData(aHidd_UHCI_PCIDevice, 0, msg->attrList);
354 uhci->pciDriver = (OOP_Object *)GetTagData(aHidd_UHCI_PCIDriver, 0, msg->attrList);
355
356 ({
357 uint32_t base = inw(uhci->iobase + UHCI_FLBASEADDR);
358 uint16_t status = inw(uhci->iobase + UHCI_STS);
359 uint16_t frame = inw(uhci->iobase + UHCI_FRNUM);
360 uint16_t port1 = inw(uhci->iobase + UHCI_PORTSC1);
361 uint16_t port2 = inw(uhci->iobase + UHCI_PORTSC2);
362 uint16_t cmd = inw(uhci->iobase + UHCI_CMD);
363 uint8_t sof = inb(uhci->iobase + UHCI_SOF);
364 int i;
365
366 bug("[UHCI] Initial state: Base=%08x Cmd=%04x SOF=%02x Status=%04x Frame=%04x PortSC1=%04x PortSC2=%04x\n",
367 base, cmd, sof, status, frame, port1, port2);
368
369 /* Windows-like BIOS detach procedure */
370 bug("[UHCI] Stopping UHCI\n");
371
372 /*
373 * Clearing RS bit will stop the controller. Clearing CF bit will tell potential
374 * legacy USB BIOS that AROS takes over
375 */
376 outw(inw(uhci->iobase + UHCI_CMD) & ~(UHCI_CMD_RS | UHCI_CMD_CF), uhci->iobase + UHCI_CMD);
377
378 for (i=0; i < 10; i++)
379 {
380 uhci_sleep(cl, o, 1);
381 if (inw(uhci->iobase + UHCI_STS) & UHCI_STS_HCH)
382 {
383 bug("[UHCI] Host controller halted\n");
384 break;
385 }
386 }
387
388 struct pHidd_PCIDevice_WriteConfigWord wcw;
389 struct pHidd_PCIDevice_ReadConfigWord rcw;
390
391 wcw.mID = OOP_GetMethodID((STRPTR)IID_Hidd_PCIDevice, moHidd_PCIDevice_WriteConfigWord);
392 wcw.reg = PCI_LEGSUP;
393 rcw.mID = OOP_GetMethodID((STRPTR)IID_Hidd_PCIDevice, moHidd_PCIDevice_ReadConfigWord);
394 rcw.reg = PCI_LEGSUP;
395
396 uint16_t reg = OOP_DoMethod(uhci->device, (OOP_Msg)&rcw.mID);
397 bug("[UHCI] PCI_LEGSUP=%04x -> ", reg);
398 reg &= 0xffef;
399 wcw.val = reg;
400 bug("%04x\n", reg);
401 OOP_DoMethod(uhci->device, (OOP_Msg)&wcw.mID);
402 reg = OOP_DoMethod(uhci->device, (OOP_Msg)&rcw.mID);
403 bug("[UHCI] PCI_LEGSUP=%04x\n", reg);
404 wcw.val = 0x2000;
405 OOP_DoMethod(uhci->device, (OOP_Msg)&wcw.mID);
406 reg = OOP_DoMethod(uhci->device, (OOP_Msg)&rcw.mID);
407 bug("[UHCI] PCI_LEGSUP=%04x\n", reg);
408 });
409
410
411
412 OOP_GetAttr(uhci->device, aHidd_PCIDevice_INTLine, &uhci->irq);
413
414 D(bug("[UHCI] New driver with IOBase=%x, IRQ=%d, PCI device=%08x, PCI driver=%08x\n",
415 uhci->iobase, uhci->irq, uhci->device, uhci->pciDriver));
416
417 uhci->Frame = HIDD_PCIDriver_AllocPCIMem(uhci->pciDriver, 4096);
418 D(bug("[UHCI] Frame = %08x\n", uhci->Frame));
419
420 outl((uint32_t)uhci->Frame, uhci->iobase + UHCI_FLBASEADDR);
421
422 uhci->irqHandler.is_Node.ln_Type = NT_INTERRUPT;
423 uhci->irqHandler.is_Node.ln_Name = "UHCI Intr";
424 uhci->irqHandler.is_Node.ln_Pri = 127;
425 uhci->irqHandler.is_Code = (VOID_FUNC)uhci_Handler;
426 uhci->irqHandler.is_Data = uhci;
427
428 AddIntServer(INTB_KERNEL + uhci->irq, &uhci->irqHandler);
429 D(bug("[UHCI] IRQHandler = %08x\n", &uhci->irqHandler));
430
431 struct pHidd_PCIDevice_WriteConfigWord __msg = {
432 OOP_GetMethodID((STRPTR)IID_Hidd_PCIDevice, moHidd_PCIDevice_WriteConfigWord), 0xc0, 0x8f00
433 }, *msg = &__msg;
434
435 OOP_DoMethod(uhci->device, (OOP_Msg)msg);
436
437 D(bug("[UHCI] Preparing initial QH tree\n"));
438
439 uhci->dummy_td = uhci_AllocTD(cl, o);
440 uhci->dummy_td->td_Buffer = 0;
441 uhci->dummy_td->td_LinkPtr = 0;
442 uhci->dummy_td->td_Status = 0;
443 uhci->dummy_td->td_Token = 0;
444
445 uhci->qh01 = uhci_AllocQH(cl, o);
446 uhci->qh01->qh_VLink = UHCI_PTR_T;
447 uhci->qh01->qh_HLink = UHCI_PTR_T;
448
449 for (i=0; i < 2; i++)
450 {
451 uhci->qh02[i] = uhci_AllocQH(cl, o);
452 uhci->qh02[i]->qh_VLink = UHCI_PTR_T;
453 uhci->qh02[i]->qh_HLink = UHCI_PTR_QH | (uint32_t)uhci->qh01;
454 }
455
456 for (i=0; i < 4; i++)
457 {
458 uhci->qh04[i] = uhci_AllocQH(cl, o);
459 uhci->qh04[i]->qh_VLink = UHCI_PTR_T;
460 uhci->qh04[i]->qh_HLink = UHCI_PTR_QH | (uint32_t)uhci->qh02[i & 0x01];
461 }
462
463 for (i=0; i < 8; i++)
464 {
465 uhci->qh08[i] = uhci_AllocQH(cl, o);
466 uhci->qh08[i]->qh_VLink = UHCI_PTR_T;
467 uhci->qh08[i]->qh_HLink = UHCI_PTR_QH | (uint32_t)uhci->qh04[i & 0x03];
468 }
469
470 for (i=0; i < 16; i++)
471 {
472 uhci->qh16[i] = uhci_AllocQH(cl, o);
473 uhci->qh16[i]->qh_VLink = UHCI_PTR_T;
474 uhci->qh16[i]->qh_HLink = UHCI_PTR_QH | (uint32_t)uhci->qh08[i & 0x07];
475 }
476
477 for (i=0; i < 32; i++)
478 {
479 uhci->qh32[i] = uhci_AllocQH(cl, o);
480 uhci->qh32[i]->qh_VLink = UHCI_PTR_T;
481 uhci->qh32[i]->qh_HLink = UHCI_PTR_QH | (uint32_t)uhci->qh16[i & 0x0f];
482 }
483
484 for (i=0; i < 1024; i++) {
485 uhci->Frame[i] = UHCI_PTR_QH | (uint32_t)uhci->qh32[i % 0x1f];
486 }
487
488 D(bug("[UHCI] Enabling the controller\n"));
489
490 outw(0, uhci->iobase + UHCI_INTR);
491 uhci_globalreset(cl, o);
492 uhci_reset(cl, o);
493
494 struct pHidd_PCIDevice_WriteConfigWord __msg2 = {
495 OOP_GetMethodID((STRPTR)IID_Hidd_PCIDevice, moHidd_PCIDevice_WriteConfigWord), 0xc0, 0x2000
496 }, *msg2 = &__msg2;
497
498 OOP_DoMethod(uhci->device, (OOP_Msg)msg2);
499
500 outb(0x40, uhci->iobase + UHCI_SOF);
501
502 outw(0, uhci->iobase + UHCI_FRNUM);
503 outl((uint32_t)uhci->Frame, uhci->iobase + UHCI_FLBASEADDR);
504
505 outw(UHCI_CMD_MAXP | UHCI_CMD_CF, uhci->iobase + UHCI_CMD);
506
507 outw(UHCI_INTR_SPIE | UHCI_INTR_IOCE | UHCI_INTR_RIE | UHCI_INTR_TOCRCIE,
508 uhci->iobase + UHCI_INTR );
509 }
510
511
512 D(bug("[UHCI] UHCI::New() = %p\n",o));
513
514 if (!o)
515 BASE(cl->UserData)->LibNode.lib_OpenCnt--;
516
517 return o;
518 }
519
520 void METHOD(UHCI, Root, Dispose)
521 {
522 UHCIData *uhci = OOP_INST_DATA(cl, o);
523 struct uhcibase *base = BASE(cl->UserData);
524
525 D(bug("[UHCI] UHCI::Dispose\n"));
526
527 D(bug("[UHCI] Stopping USB transfer\n"));
528 outw(0, uhci->iobase + UHCI_CMD);
529
530 D(bug("[UHCI] Releasing USB ring\n"));
531 HIDD_PCIDriver_FreePCIMem(uhci->pciDriver, uhci->Frame);
532
533 D(bug("[UHCI] Removing IRQ handler\n"));
534 RemIntServer(INTB_KERNEL + uhci->irq, &uhci->irqHandler);
535
536 AbortIO((struct IORequest *)uhci->timereq);
537 DeleteIORequest((struct IORequest *)uhci->timereq);
538
539 struct MsgPort *port = uhci->tr->tr_node.io_Message.mn_ReplyPort;
540 port->mp_SigTask = FindTask(NULL);
541 CloseDevice((struct IORequest *)uhci->tr);
542 DeleteIORequest((struct IORequest *)uhci->tr);
543 port->mp_SigBit = AllocSignal(-1);
544 DeleteMsgPort(port);
545
546 OOP_DoSuperMethod(cl, o, (OOP_Msg)msg);
547
548 base->LibNode.lib_OpenCnt--;
549 }
550
551 void METHOD(UHCI, Root, Get)
552 {
553 uint32_t idx;
554
555 if (IS_USBDEVICE_ATTR(msg->attrID, idx))
556 {
557 switch (idx)
558 {
559 case aoHidd_USBDevice_Address:
560 *msg->storage = 1;
561 break;
562 case aoHidd_USBDevice_Hub:
563 *msg->storage = 0;
564 break;
565 case aoHidd_USBDevice_Bus:
566 *msg->storage = (IPTR)o;
567 break;
568 default:
569 OOP_DoSuperMethod(cl, o, (OOP_Msg)msg);
570 }
571 }
572 else if (IS_USBDRV_ATTR(msg->attrID, idx))
573 {
574
575 }
576 else
577 OOP_DoSuperMethod(cl, o, (OOP_Msg)msg);
578 }
579
580 void METHOD(UHCI, Root, Set)
581 {
582 uint32_t idx;
583 struct TagItem *tag;
584 struct TagItem *tags = msg->attrList;
585
586 while ((tag = NextTagItem(&tags)))
587 {
588 if (IS_USBDEVICE_ATTR(tag->ti_Tag, idx))
589 {
590 }
591 else if (IS_USBHUB_ATTR(tag->ti_Tag, idx))
592 {
593
594 }
595 else if (IS_USBDRV_ATTR(tag->ti_Tag, idx))
596 {
597 }
598 }
599
600 OOP_DoSuperMethod(cl, o, (OOP_Msg)msg);
601 }
602
603
604 APTR METHOD(UHCI, Hidd_USBDrv, CreatePipe)
605 {
606 return uhci_CreatePipe(cl, o, msg->type, msg->fullspeed, msg->address, msg->endpoint, msg->period, msg->maxpacket, msg->timeout);
607 }
608
609 void METHOD(UHCI, Hidd_USBDrv, DeletePipe)
610 {
611 return uhci_DeletePipe(cl, o, msg->pipe);
612 }
613
614 void METHOD(UHCI, Hidd_USBDrv, SetTimeout)
615 {
616 UHCI_Pipe *p = msg->pipe;
617
618 if (p)
619 p->p_TimeoutVal = msg->timeout;
620 }
621
622 BOOL METHOD(UHCI, Hidd_USBDrv, AddInterrupt)
623 {
624 BOOL retval = FALSE;
625 UHCI_Pipe *p = msg->pipe;
626
627 if (msg->pipe == (APTR)0xdeadbeef)
628 {
629 UHCIData *uhci = OOP_INST_DATA(cl, o);
630 D(bug("[UHCI] AddInterrupt() local for the UHCI. Intr %p, list %p\n", msg->interrupt, &uhci->intList));
631
632 if (!uhci->iobase)
633 uhci->tmp = msg->interrupt;
634 else
635 AddTail(&uhci->intList, &msg->interrupt->is_Node);
636
637 retval = TRUE;
638 }
639 else
640 {
641 D(bug("[UHCI] AddInterrupt()\n"));
642
643 UHCI_Interrupt_t *intr = AllocVecPooled(SD(cl)->MemPool, sizeof(UHCI_Interrupt_t));
644
645 D(bug("[UHCI::AddInterrupt] intr = %p\n", intr));
646
647 if (intr)
648 {
649 intr->i_intr = msg->interrupt;
650
651 uhci_QueuedRead(cl, o, p, msg->buffer, msg->length);
652 AddTail((struct List *)&p->p_Intr, (struct Node *)&intr->i_node);
653
654 /*
655 intr->i_td = uhci_AllocTD(cl, o);
656
657 D(bug("[UHCI::AddInterrupt] intr->i_td = %p\n", intr->i_td));
658
659 if (intr->i_td)
660 {
661 intr->i_td->td_Buffer = (uint32_t)msg->buffer;
662 intr->i_td->td_Status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
663 intr->i_td->td_Token = UHCI_TD_IN(msg->length, p->p_EndPoint, p->p_DevAddr, p->p_NextToggle);
664 intr->i_td->td_Status |= UHCI_TD_SPD;
665 intr->i_td->td_LinkPtr = UHCI_PTR_T;
666
667 Disable();
668
669 AddTail(&p->p_Intr, &intr->i_node);
670
671 if (p->p_FirstTD == (APTR)UHCI_PTR_T)
672 {
673 p->p_FirstTD = intr->i_td;
674 p->p_LastTD = intr->i_td;
675 }
676 else
677 {
678 p->p_LastTD->td_LinkPtr = (uint32_t)intr->i_td | UHCI_PTR_TD;
679 p->p_LastTD = intr->i_td;
680 }
681
682 if (p->p_Queue->qh_VLink == UHCI_PTR_T)
683 {
684 p->p_Queue->qh_VLink = (uint32_t)p->p_FirstTD | UHCI_PTR_TD;
685 }
686
687 Enable();
688
689 bug("[UHCI::AddInterrupt] p->p_FirstTd = %p, vlink=%p\n", p->p_FirstTD, p->p_Queue->qh_VLink);
690 retval = TRUE;
691 }
692 else
693 FreeVecPooled(SD(cl)->MemPool, intr);
694 */
695 }
696 }
697 D(bug("[UHCI::AddInterrupt] %s\n", retval ? "success":"failure"));
698
699 return retval;
700 }
701
702 BOOL METHOD(UHCI, Hidd_USBDrv, RemInterrupt)
703 {
704 UHCI_Interrupt_t *intr;
705 UHCI_Pipe *p = msg->pipe;
706
707 if (p == (UHCI_Pipe *)0xdeadbeef)
708 {
709 Remove((struct Node *)msg->interrupt);
710 return TRUE;
711 }
712 else
713 {
714 ForeachNode(&p->p_Intr, intr)
715 {
716 if (intr->i_intr == msg->interrupt)
717 break;
718 }
719
720 if (intr)
721 {
722 Disable();
723 Remove((struct Node *)&intr->i_node);
724 Enable();
725
726 uhci_FreeTD(cl, o, intr->i_td);
727 FreeVecPooled(SD(cl)->MemPool, intr);
728
729 return TRUE;
730 }
731 return FALSE;
732 }
733 }
734
735 BOOL METHOD(UHCI, Hidd_USBDrv, ControlTransfer)
736 {
737 UHCI_Pipe *p = msg->pipe;
738 D(UHCIData *uhci = OOP_INST_DATA(cl, o));
739
740 BOOL retval = TRUE;
741
742 D({
743 uint16_t status = inw(uhci->iobase + UHCI_STS);
744 uint16_t frame = inw(uhci->iobase + UHCI_FRNUM);
745 uint16_t port1 = inw(uhci->iobase + UHCI_PORTSC1);
746 uint16_t port2 = inw(uhci->iobase + UHCI_PORTSC2);
747 uint16_t cmd = inw(uhci->iobase + UHCI_CMD);
748 uint16_t sof = inb(uhci->iobase + UHCI_SOF);
749
750 D(bug("[UHCI] Status check: Cmd=%04x, SOF=%04x, Status = %04x, Frame=%04x, PortSC1=%04x, PortSC2=%04x\n",
751 cmd, sof, status, frame, port1, port2));
752 });
753
754 int8_t sig = AllocSignal(-1);
755 int8_t toutsig = AllocSignal(-1);
756 int32_t msec = p->p_TimeoutVal;
757
758 D(bug("[UHCI] ControlTransfer(pipe=%p, request=%p, buffer=%p, length=%d, timeout=%d, signal=%d, toutsig=%d)\n",
759 msg->pipe, msg->request, msg->buffer, msg->length, msec, sig, toutsig));
760
761 if (sig >= 0 && toutsig >= 0)
762 {
763 p->p_Signal = sig;
764 p->p_SigTask = FindTask(NULL);
765
766 if (p->p_TimeoutVal != 0)
767 {
768 p->p_Timeout->tr_node.io_Message.mn_ReplyPort->mp_SigBit = toutsig;
769 p->p_Timeout->tr_node.io_Message.mn_ReplyPort->mp_SigTask = FindTask(NULL);
770
771 p->p_Timeout->tr_node.io_Command = TR_ADDREQUEST;
772 p->p_Timeout->tr_time.tv_secs = msec / 1000;
773 p->p_Timeout->tr_time.tv_micro = 1000 * (msec % 1000);
774
775 SendIO((struct IORequest *)p->p_Timeout);
776 }
777 uhci_ControlTransfer(cl, o, msg->pipe, msg->request, msg->buffer, msg->length);
778 if (Wait((1 << sig) | (1 << toutsig)) & (1 << toutsig))
779 {
780 bug("[UHCI] !!!TIMEOUT!!!\n");
781 p->p_Queue->qh_VLink = UHCI_PTR_T;
782 UHCI_TransferDesc *td = (UHCI_TransferDesc *)p->p_FirstTD;
783
784 GetMsg(p->p_Timeout->tr_node.io_Message.mn_ReplyPort);
785
786 while ((uint32_t)td != UHCI_PTR_T)
787 {
788 bug("[UHCI] TD=%p (%08x %08x %08x %08x)\n", td,
789 td->td_LinkPtr, td->td_Status, td->td_Token, td->td_Buffer);
790 UHCI_TransferDesc *tnext = (UHCI_TransferDesc *)(td->td_LinkPtr & 0xfffffff1);
791 uhci_FreeTD(cl, o, td);
792 td = tnext;
793 p->p_FirstTD = tnext;
794 }
795 p->p_LastTD=(APTR)UHCI_PTR_T;
796
797 retval = FALSE;
798 }
799 else
800 {
801 if (!CheckIO((struct IORequest *)p->p_Timeout))
802 AbortIO((struct IORequest *)p->p_Timeout);
803 WaitIO((struct IORequest *)p->p_Timeout);
804 SetSignal(0, 1 << toutsig);
805
806 if (p->p_ErrorCode)
807 retval = FALSE;
808 }
809 FreeSignal(sig);
810 FreeSignal(toutsig);
811 }
812 return retval;
813 }
814
815 BOOL METHOD(UHCI, Hidd_USBDrv, BulkTransfer)
816 {
817 UHCI_Pipe *p = msg->pipe;
818
819 BOOL retval = TRUE;
820
821 int8_t sig = AllocSignal(-1);
822 int8_t toutsig = AllocSignal(-1);
823 int32_t msec = p->p_TimeoutVal;
824
825 D(bug("[UHCI] BulkTransfer(pipe=%p, buffer=%p, length=%d, timeout=%d, signal=%d, toutsig=%d)\n",
826 msg->pipe, msg->buffer, msg->length, msec, sig, toutsig));
827
828 if (sig >= 0 && toutsig >= 0)
829 {
830 p->p_Signal = sig;
831 p->p_SigTask = FindTask(NULL);
832
833 if (p->p_TimeoutVal != 0)
834 {
835 p->p_Timeout->tr_node.io_Message.mn_ReplyPort->mp_SigBit = toutsig;
836 p->p_Timeout->tr_node.io_Message.mn_ReplyPort->mp_SigTask = FindTask(NULL);
837
838 p->p_Timeout->tr_node.io_Command = TR_ADDREQUEST;
839 p->p_Timeout->tr_time.tv_secs = msec / 1000;
840 p->p_Timeout->tr_time.tv_micro = 1000 * (msec % 1000);
841
842 SendIO((struct IORequest *)p->p_Timeout);
843 }
844
845 uhci_QueuedTransfer(cl, o, p, msg->buffer, msg->length, p->p_EndPoint & 0x80);
846
847 if (Wait((1 << sig) | (1 << toutsig)) & (1 << toutsig))
848 {
849 bug("[UHCI] !!!TIMEOUT!!!\n");
850 p->p_Queue->qh_VLink = UHCI_PTR_T;
851 UHCI_TransferDesc *td = (UHCI_TransferDesc *)p->p_FirstTD;
852
853 GetMsg(p->p_Timeout->tr_node.io_Message.mn_ReplyPort);
854
855 while ((uint32_t)td != UHCI_PTR_T)
856 {
857 bug("[UHCI] TD=%p (%08x %08x %08x %08x)\n", td,
858 td->td_LinkPtr, td->td_Status, td->td_Token, td->td_Buffer);
859 UHCI_TransferDesc *tnext = (UHCI_TransferDesc *)(td->td_LinkPtr & 0xfffffff1);
860 uhci_FreeTD(cl, o, td);
861 td = tnext;
862 p->p_FirstTD = tnext;
863 }
864 p->p_LastTD=(APTR)UHCI_PTR_T;
865
866 retval = FALSE;
867 }
868 else
869 {
870 if (!CheckIO((struct IORequest *)p->p_Timeout))
871 AbortIO((struct IORequest *)p->p_Timeout);
872 WaitIO((struct IORequest *)p->p_Timeout);
873 SetSignal(0, 1 << toutsig);
874
875 if (p->p_ErrorCode)
876 retval = FALSE;
877 }
878 FreeSignal(sig);
879 FreeSignal(toutsig);
880 }
881
882 D({
883 if (retval)
884 (bug("[UHCI] Transfer OK\n"));
885 else
886 (bug("[UHCI] Transfer FAILED\n"));
887 });
888
889 return retval;
890 }
891
892 BOOL METHOD(UHCI, Hidd_USBHub, OnOff)
893 {
894 UHCIData *uhci = OOP_INST_DATA(cl, o);
895 BOOL retval;
896 D(bug("[UHCI] USBHub::OnOff(%d)\n", msg->on));
897
898 if (!CheckIO((struct IORequest *)uhci->timereq))
899 AbortIO((struct IORequest *)uhci->timereq);
900 GetMsg(&uhci->mport);
901 SetSignal(0, 1 << uhci->mport.mp_SigBit);
902
903 uhci->running = msg->on;
904
905 if (msg->on)
906 {
907 uhci->timereq->tr_node.io_Command = TR_ADDREQUEST;
908 uhci->timereq->tr_time.tv_secs = 1;
909 uhci->timereq->tr_time.tv_micro = 0;
910 SendIO((struct IORequest *)uhci->timereq);
911 }
912
913 OOP_DoSuperMethod(cl,o,(OOP_Msg)msg);
914
915 retval = uhci_run(cl, o, msg->on);
916 uhci_sleep(cl, o, 100);
917
918 return retval;
919 }
920
921 BOOL METHOD(UHCI, Hidd_USBHub, PortReset)
922 {
923 UHCIData *uhci = OOP_INST_DATA(cl, o);
924 BOOL retval;
925 D(bug("[UHCI] USBHub::PortReset(%d)\n", msg->portNummer));
926 retval = uhci_PortReset(cl, o, msg->portNummer);
927 uhci->reset |= (1 << (msg->portNummer - 1));
928 uhci_sleep(cl, o, 100);
929 return retval;
930 }
931
932 BOOL METHOD(UHCI, Hidd_USBHub, GetPortStatus)
933 {
934 UHCIData *uhci = OOP_INST_DATA(cl, o);
935 uint16_t port, x, status=0, change=0;
936
937 if (msg->port == 1)
938 port = UHCI_PORTSC1;
939 else if (msg->port == 2)
940 port = UHCI_PORTSC2;
941 else return FALSE;
942
943 x = inw(uhci->iobase + port);
944
945 if (x & UHCI_PORTSC_CCS)
946 status |= UPS_CURRENT_CONNECT_STATUS;
947 if (x & UHCI_PORTSC_CSC)
948 change |= UPS_C_CONNECT_STATUS;
949 if (x & UHCI_PORTSC_PE)
950 status |= UPS_PORT_ENABLED;
951 if (x & UHCI_PORTSC_POEDC)
952 change |= UPS_C_PORT_ENABLED;
953 if (x & UHCI_PORTSC_OCI)
954 status |= UPS_OVERCURRENT_INDICATOR;
955 if (x & UHCI_PORTSC_OCIC)
956 change |= UPS_C_OVERCURRENT_INDICATOR;
957 if (x & UHCI_PORTSC_SUSP)
958 status |= UPS_SUSPEND;
959 if (x & UHCI_PORTSC_LSDA)
960 status |= UPS_LOW_SPEED;
961
962 status |= UPS_PORT_POWER;
963
964 if (uhci->reset & (1 << (msg->port - 1)))
965 status |= UPS_C_PORT_RESET;
966
967 msg->status->wPortStatus = AROS_WORD2LE(status);
968 msg->status->wPortChange = AROS_WORD2LE(change);
969
970 return TRUE;
971 }
972
973 BOOL METHOD(UHCI, Hidd_USBHub, GetHubStatus)
974 {
975 return TRUE;
976 }
977
978 BOOL METHOD(UHCI, Hidd_USBHub, ClearHubFeature)
979 {
980 return TRUE;
981 }
982
983 BOOL METHOD(UHCI, Hidd_USBHub, SetHubFeature)
984 {
985 return TRUE;
986 }
987
988 BOOL METHOD(UHCI, Hidd_USBHub, ClearPortFeature)
989 {
990 UHCIData *uhci = OOP_INST_DATA(cl, o);
991 uint16_t port, x;
992 BOOL retval = FALSE;
993
994 if (msg->port == 1)
995 port = UHCI_PORTSC1;
996 else if (msg->port == 2)
997 port = UHCI_PORTSC2;
998 else return FALSE;
999
1000 switch(msg->feature)
1001 {
1002 case UHF_PORT_ENABLE:
1003 x = URWMASK(inw(uhci->iobase + port));
1004 outw(x & ~UHCI_PORTSC_PE, uhci->iobase + port);
1005 retval = TRUE;
1006 break;
1007
1008 case UHF_PORT_SUSPEND:
1009 x = URWMASK(inw(uhci->iobase + port));
1010 outw(x & ~UHCI_PORTSC_SUSP, uhci->iobase + port);
1011 retval = TRUE;
1012 break;
1013
1014 case UHF_PORT_RESET:
1015 x = URWMASK(inw(uhci->iobase + port));
1016 outw(x & ~UHCI_PORTSC_PR, uhci->iobase + port);
1017 retval = TRUE;
1018 break;
1019
1020 case UHF_C_PORT_CONNECTION:
1021 x = URWMASK(inw(uhci->iobase + port));
1022 outw(x | UHCI_PORTSC_CSC, uhci->iobase + port);
1023 retval = TRUE;
1024 break;
1025
1026 case UHF_C_PORT_ENABLE:
1027 x = URWMASK(inw(uhci->iobase + port));
1028 outw(x | UHCI_PORTSC_POEDC, uhci->iobase + port);
1029 retval = TRUE;
1030 break;
1031
1032 case UHF_C_PORT_OVER_CURRENT:
1033 x = URWMASK(inw(uhci->iobase + port));
1034 outw(x | UHCI_PORTSC_OCIC, uhci->iobase + port);
1035 retval = TRUE;
1036 break;
1037
1038 case UHF_C_PORT_RESET:
1039 uhci->reset &= ~(1 << (msg->port - 1));
1040 retval = TRUE;
1041 break;
1042
1043 default:
1044 retval = FALSE;
1045 break;
1046 }
1047
1048 return retval;
1049 }
1050
1051 BOOL METHOD(UHCI, Hidd_USBHub, SetPortFeature)
1052 {
1053 UHCIData *uhci = OOP_INST_DATA(cl, o);
1054 uint16_t port, x;
1055 BOOL retval = FALSE;
1056
1057 if (msg->port == 1)
1058 port = UHCI_PORTSC1;
1059 else if (msg->port == 2)
1060 port = UHCI_PORTSC2;
1061 else return FALSE;
1062
1063 switch(msg->feature)
1064 {
1065 case UHF_PORT_ENABLE:
1066 x = URWMASK(inw(uhci->iobase + port));
1067 outw(x | UHCI_PORTSC_PE, uhci->iobase + port);
1068 retval = TRUE;
1069 break;
1070
1071 case UHF_PORT_SUSPEND:
1072 x = URWMASK(inw(uhci->iobase + port));
1073 outw(x | UHCI_PORTSC_SUSP, uhci->iobase + port);
1074 retval = TRUE;
1075 break;
1076
1077 case UHF_PORT_RESET:
1078 retval = uhci_PortReset(cl, o, msg->port);
1079 break;
1080
1081 case UHF_PORT_POWER:
1082 retval = TRUE;
1083 break;
1084
1085 default:
1086 retval = FALSE;
1087 break;
1088 }
1089
1090 return retval;
1091 }
1092
1093 static const char *string1 = "U\0H\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B";
1094 static const int string1_l = sizeof("U\0H\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B");
1095
1096 static const char *string2 = "T\0h\0e\0 \0A\0R\0O\0S\0 \0D\0e\0v\0e\0l\0o\0p\0m\0e\0n\0t\0 \0T\0e\0a\0m";
1097 static const int string2_l = sizeof("T\0h\0e\0 \0A\0R\0O\0S\0 \0D\0e\0v\0e\0l\0o\0p\0m\0e\0n\0t\0 \0T\0e\0a\0m");
1098
1099 BOOL METHOD(UHCI, Hidd_USBDevice, GetString)
1100 {
1101 msg->string->bDescriptorType = UDESC_STRING;
1102
1103 if (msg->id == USB_LANGUAGE_TABLE)
1104 {
1105 msg->string->bLength = 4;
1106 msg->string->bString[0] = 0x0409;
1107 }
1108 else if (msg->id == 1)
1109 {
1110 msg->string->bLength = 2 + string1_l;
1111 CopyMem(string1, &msg->string->bString[0], string1_l);
1112 }
1113 else if (msg->id == 2)
1114 {
1115 msg->string->bLength = 2 + string2_l;
1116 CopyMem(string2, &msg->string->bString[0], string2_l);
1117 }
1118 else if (msg->id == 3)
1119 {
1120 char buff[129];
1121 int i;
1122 snprintf(buff, 128, "%d.%d", VERSION_NUMBER, REVISION_NUMBER);
1123 msg->string->bLength = 2 + 2*strlen(buff);
1124 for (i=0; i < ((msg->string->bLength - 2) >> 1); i++)
1125 msg->string->bString[i] = AROS_WORD2LE(buff[i]);
1126 }
1127 else
1128 {
1129 return FALSE;
1130 }
1131 return TRUE;
1132 }
1133
1134 static const usb_device_descriptor_t device_descriptor = {
1135 bLength: sizeof(usb_device_descriptor_t),
1136 bDescriptorType: UDESC_DEVICE,
1137 bcdUSB: 0x0101,
1138 bDeviceClass: UDCLASS_HUB,
1139 bDeviceSubClass: UDSUBCLASS_HUB,
1140 bDeviceProtocol: UDPROTO_FSHUB,
1141 bMaxPacketSize: 64,
1142 iManufacturer: 2,
1143 iProduct: 1,
1144 iSerialNumber: 3,
1145 bNumConfigurations: 1,
1146 };
1147
1148 static const usb_hub_descriptor_t hub_descriptor = {
1149 bDescLength: sizeof(usb_hub_descriptor_t) - 31,
1150 bDescriptorType: UDESC_HUB,
1151 bNbrPorts: 2,
1152 wHubCharacteristics:0,
1153 bPwrOn2PwrGood: 50,
1154 bHubContrCurrent: 0,
1155 DeviceRemovable: {0,},
1156 };
1157
1158 static const usb_endpoint_descriptor_t endpoint_descriptor = {
1159 bLength: sizeof(usb_endpoint_descriptor_t),
1160 bDescriptorType: UDESC_ENDPOINT,
1161 bEndpointAddress: 0x81,
1162 bmAttributes: 0x03,
1163 wMaxPacketSize: 1,
1164 bInterval: 255
1165 };
1166
1167 usb_endpoint_descriptor_t * METHOD(UHCI, Hidd_USBDevice, GetEndpoint)
1168 {
1169 if (msg->interface == 0 && msg->endpoint == 0)
1170 return (usb_endpoint_descriptor_t *)&endpoint_descriptor;
1171 else
1172 return NULL;
1173 }
1174
1175 BOOL METHOD(UHCI, Hidd_USBDevice, GetDeviceDescriptor)
1176 {
1177 CopyMem(&device_descriptor, msg->descriptor, sizeof(device_descriptor));
1178 return TRUE;
1179 }
1180
1181 BOOL METHOD(UHCI, Hidd_USBHub, GetHubDescriptor)
1182 {
1183 CopyMem(&hub_descriptor, msg->descriptor, sizeof(hub_descriptor));
1184 msg->descriptor->wHubCharacteristics = AROS_WORD2LE(UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL);
1185 return TRUE;
1186 }
1187
1188 BOOL METHOD(UHCI, Hidd_USBDevice, Configure)
1189 {
1190 D(bug("[UHCI] ::Configure(%d)", msg->configNr));
1191 return TRUE;
1192 }
1193
1194 APTR METHOD(UHCI, Hidd_USBDevice, CreatePipe)
1195 {
1196 if ( (msg->type == PIPE_Interrupt) &&
1197 (msg->endpoint == 0x81))
1198 return (APTR)0xdeadbeef;
1199 else
1200 return NULL;
1201 }
1202
1203 void METHOD(UHCI, Hidd_USBDevice, DeletePipe)
1204 {
1205 }
1206
1207 void METHOD(UHCI, Hidd_USBDevice, SetTimeout)
1208 {
1209 }
1210
1211 /* Class initialization and destruction */
1212
1213 #undef SD
1214 #define SD(x) (&LIBBASE->sd)
1215
1216 static int UHCI_InitClass(LIBBASETYPEPTR LIBBASE)
1217 {
1218 int i;
1219 D(bug("[UHCI] InitClass\n"));
1220
1221 HiddUHCIAttrBase = OOP_ObtainAttrBase(IID_Drv_USB_UHCI);
1222
1223 if (HiddUHCIAttrBase)
1224 {
1225 struct TagItem tags[] = {
1226 { aHidd_UHCI_IOBase, 0UL },
1227 { aHidd_UHCI_PCIDevice, 0UL },
1228 { aHidd_UHCI_PCIDriver, 0UL },
1229 { aHidd_USBDevice_Address, 1UL },
1230 { aHidd_USBHub_IsRoot, 1UL },
1231 { aHidd_USBHub_NumPorts, 2UL },
1232 { TAG_DONE, 0UL },
1233 };
1234
1235 for (i=0; i < LIBBASE->sd.num_devices; i++)
1236 {
1237 tags[0].ti_Data = LIBBASE->sd.iobase[i];
1238 tags[1].ti_Data = (IPTR)LIBBASE->sd.uhciDevice[i];
1239 tags[2].ti_Data = (IPTR)LIBBASE->sd.uhciPCIDriver[i];
1240 LIBBASE->sd.uhciDevice[i] = OOP_NewObject(NULL, CLID_Drv_USB_UHCI, tags);
1241 HIDD_USB_AttachDriver(LIBBASE->sd.usb, LIBBASE->sd.uhciDevice[i]);
1242 }
1243 }
1244
1245 return TRUE;
1246 }
1247
1248 static int UHCI_ExpungeClass(LIBBASETYPEPTR LIBBASE)
1249 {
1250 D(bug("[UHCI] ExpungeClass\n"));
1251
1252 OOP_ReleaseAttrBase(IID_Drv_USB_UHCI);
1253
1254 return TRUE;
1255 }
1256
1257 ADD2INITLIB(UHCI_InitClass, 0)
1258 ADD2EXPUNGELIB(UHCI_ExpungeClass, 0)
Mirror of AROS' svn.