Enable FIQ interrupt handling on BCM mailboxes. Each CPU core has four of them and...
[AROS.git] / arch / arm-native / kernel / tls.h
blob8eaba7fa2abc23069b07c90f708a2e88aad8c2d3
1 #ifndef ASM_TLS_H
2 #define ASM_TLS_H
4 typedef struct tls
6 struct ExecBase *SysBase;
7 void * *KernelBase; /* Base of kernel.resource */
8 struct Task *ThisTask; /* Currently running task on this core */
9 } tls_t;
11 #define TLS_OFFSET(name) ((char *)&(((tls_t *)0)->name)-(char *)0)
13 ////
15 #define TLS_GET(name) \
16 ({ \
17 tls_t *__tls; \
18 asm volatile("mrc p15, 0, %0, c13, c0, 3":"=r"(__tls)); \
19 typeof(__tls -> name) __ret = (__tls -> name); \
20 __ret; \
23 #define TLS_SET(name, val) \
24 do { \
25 tls_t *__tls; \
26 asm volatile("mrc p15, 0, %0, c13, c0, 3":"=r"(__tls)); \
27 (__tls -> name) = val; \
28 } while(0);
30 #endif