Enable FIQ interrupt handling on BCM mailboxes. Each CPU core has four of them and...
[AROS.git] / arch / arm-native / kernel / kernel_cpu.h
blob4202724a3b1159a15556a581e08a43e75199ddd6
1 /*
2 Copyright © 2013, The AROS Development Team. All rights reserved.
3 $Id$
4 */
6 #ifndef CPU_ARM_H_
7 #define CPU_ARM_H_
9 #include <inttypes.h>
11 extern uint32_t __arm_affinitymask;
13 #define EXCEPTIONS_COUNT 1
15 #define ARM_FPU_TYPE FPU_VFP
16 #define ARM_FPU_SIZE 32*64
18 /* We use native context format, no conversion needed */
19 #define regs_t struct ExceptionContext
20 /* There are no private add-ons */
21 #define AROSCPUContext ExceptionContext
23 #define goSuper() 0
24 #define goUser()
26 #define krnSysCall(n) asm volatile ("swi %[swi_no]\n\t" : : [swi_no] "I" (n) : "lr");
28 void cpu_DumpRegs(regs_t *regs);
30 #endif /* CPU_ARM_H_ */