Enable FIQ interrupt handling on BCM mailboxes. Each CPU core has four of them and...
[AROS.git] / arch / arm-native / kernel / intvecs.s
blob2fd81c7344ee145383e2f15a37ac857fdc2e4802
2 .section .intvecs, "ax"
4 /* initial, unpatchable vector table */
6 _reset_vec:
7 ldr pc, reset_handler_address
8 ldr pc, undef_handler_address
9 ldr pc, svc_handler_address
10 ldr pc, prefetch_abort_handler_address
11 ldr pc, data_abort_handler_address
12 _loop: b .
13 ldr pc, irq_handler_address
14 ldr pc, fiq_handler_address
16 reset_handler_address: .word __vectorhand_reset
17 undef_handler_address: .word __vectorhand_undef
18 svc_handler_address: .word __vectorhand_swi
19 prefetch_abort_handler_address: .word __vectorhand_prefetchabort
20 data_abort_handler_address: .word __vectorhand_dataabort
21 irq_handler_address: .word __vectorhand_irq
22 fiq_handler_address: .word __vectorhand_fiq