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wip prep commit in lieu of gfx subsystem update changes.
[AROS.git] / workbench / hidds / nvidia / nvidia_init.c
blobe2361cdef6ded6860ef2b077a852cc348688e4aa
1 /*
2 Copyright © 2004-2017, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc: nvidia.hidd initialization
6 Lang: English
7 */
8
9 /***************************************************************************\
10 |* *|
11 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
12 |* *|
13 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
14 |* international laws. Users and possessors of this source code are *|
15 |* hereby granted a nonexclusive, royalty-free copyright license to *|
16 |* use this code in individual and commercial software. *|
17 |* *|
18 |* Any use of this source code must include, in the user documenta- *|
19 |* tion and internal comments to the code, notices to the end user *|
20 |* as follows: *|
21 |* *|
22 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
23 |* *|
24 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
25 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
26 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
27 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
28 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
29 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
30 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
31 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
33 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
34 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
35 |* *|
36 |* U.S. Government End Users. This source code is a "commercial *|
37 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
38 |* consisting of "commercial computer software" and "commercial *|
39 |* computer software documentation," as such terms are used in *|
40 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
41 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
42 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
43 |* all U.S. Government End Users acquire the source code with only *|
44 |* those rights set forth herein. *|
45 |* *|
46 \***************************************************************************/
47
48 #include <aros/libcall.h>
49 #include <aros/asmcall.h>
50
51 #include <exec/types.h>
52 #include <exec/nodes.h>
53 #include <exec/execbase.h>
54 #include <exec/resident.h>
55 #include <exec/libraries.h>
56 #include <exec/memory.h>
57 #include <exec/lists.h>
58 #include <exec/semaphores.h>
59
60 #include <dos/bptr.h>
61
62 #include <libcore/compiler.h>
63
64 #include <utility/utility.h>
65 #include <utility/hooks.h>
66 #include <utility/tagitem.h>
67
68 #include <oop/oop.h>
69
70 #include <hidd/pci.h>
71 #include <hidd/hidd.h>
72 #include <hidd/gfx.h>
73
74 #include <aros/symbolsets.h>
75
76 #define DEBUG 1
77 #include <aros/debug.h>
78
79 #include <proto/exec.h>
80 #include <proto/oop.h>
81
82 #include LC_LIBDEFS_FILE
83 #include "nv.h"
84
85 #undef HiddPCIDeviceAttrBase
86 #undef HiddGfxAttrBase
87 #undef HiddPixFmtAttrBase
88 #undef HiddSyncAttrBase
89 #undef HiddBitMapAttrBase
90 #define HiddPCIDeviceAttrBase (sd->pciAttrBase)
91 #define HiddBitMapAttrBase (sd->bitMapAttrBase)
92 #define HiddNVidiaBitMapAttrBase (sd->nvBitMapAttrBase)
93 #define HiddPixFmtAttrBase (sd->pixFmtAttrBase)
94 #define HiddGfxAttrBase (sd->gfxAttrBase)
95 #define HiddSyncAttrBase (sd->syncAttrBase)
96 #define __IHidd_PlanarBM (sd->planarAttrBase)
97
98 static BOOL GenericInit(struct staticdata *sd)
99 {
100 D(bug("[NVidia] Generic chip init\n"));
101 IPTR regs = (IPTR)sd->Card.Registers;
102 UWORD architecture = sd->Card.Architecture;
103 UWORD implementation = sd->Card.Chipset;
104 UWORD implementation_masked = implementation & 0x0FF0;
105
106 sd->Card.EnableIRQ = 0;
107 sd->Card.IO = 0x3d0;
108 sd->Card.PRAMDAC0 = (ULONG*)(regs + 0x00680000);
109 sd->Card.PFB = (ULONG*)(regs + 0x00100000);
110 sd->Card.PFIFO = (ULONG*)(regs + 0x00002000);
111 sd->Card.PGRAPH = (ULONG*)(regs + 0x00400000);
112 sd->Card.PEXTDEV = (ULONG*)(regs + 0x00101000);
113 sd->Card.PTIMER = (ULONG*)(regs + 0x00009000);
114 sd->Card.PMC = (ULONG*)(regs + 0x00000000);
115 sd->Card.FIFO = (ULONG*)(regs + 0x00800000);
116 sd->Card.PCIO0 = (UBYTE*)(regs + 0x00601000);
117 sd->Card.PDIO0 = (UBYTE*)(regs + 0x00681000);
118 sd->Card.PVIO = (UBYTE*)(regs + 0x000C0000);
119
120 sd->Card.FlatPanel = 0;
121
122 sd->Card.twoHeads = (architecture >= NV_ARCH_10) &&
123 (implementation_masked != 0x0100) &&
124 (implementation_masked != 0x0150) &&
125 (implementation_masked != 0x01A0) &&
126 (implementation_masked != 0x0200);
127
128 sd->Card.fpScaler = (sd->Card.twoHeads && (implementation_masked != 0x0110));
129
130 sd->Card.twoStagePLL = (implementation_masked == 0x0310) ||
131 (implementation_masked == 0x0340) ||
132 (architecture == NV_ARCH_40);
133
134 sd->Card.alphaCursor = implementation_masked >= 0x0110;
135
136 switch (implementation)
137 {
138 case 0x0112:
139 case 0x0174:
140 case 0x0175:
141 case 0x0176:
142 case 0x0177:
143 case 0x0179:
144 case 0x017c:
145 case 0x017d:
146 case 0x0186:
147 case 0x0187:
148 case 0x0286:
149 case 0x028c:
150 case 0x0316:
151 case 0x0317:
152 case 0x031a:
153 case 0x031b:
154 case 0x031c:
155 case 0x031d:
156 case 0x031e:
157 case 0x031f:
158 case 0x0324:
159 case 0x0325:
160 case 0x0326: /* stegerg: checkme, not listed in xfree nv_setup.c */
161 case 0x0328:
162 case 0x0329:
163 case 0x032C:
164 case 0x032D:
165 case 0x032e: /* stegerg: checkme, not listed in xfree nv_setup.c */
166 case 0x0347:
167 case 0x0349:
168 case 0x034B:
169 case 0x034C:
170 case 0x0160:
171 case 0x0166:
172 case 0x00C8:
173 case 0x00C9:
174 case 0x00CC:
175 case 0x0147:
176 case 0x0148:
177 case 0x0149:
178 case 0x014C:
179 D(bug("[NVidia] Assuming Digital FlatPanel\n"));
180 sd->Card.FlatPanel = 1;
181 break;
182 default:
183 break;
184 }
185
186 if (architecture == NV_ARCH_04)
187 nv4GetConfig(sd);
188 else
189 nv10GetConfig(sd);
190
191 NVSelectHead(sd, 0);
192
193 NVLockUnlock(sd, 0);
194
195 if (!sd->Card.twoHeads)
196 {
197 VGA_WR08(sd->Card.PCIO, 0x3d4, 0x28);
198 if (VGA_RD08(sd->Card.PCIO, 0x3d5) & 0x80)
199 sd->Card.FlatPanel = 1;
200 else
201 sd->Card.FlatPanel = 0;
202 }
203 else
204 {
205 UBYTE outputAfromCRTC, outputBfromCRTC;
206 int CRTCnumber = -1;
207 UBYTE slaved_on_A, slaved_on_B,tvA=0,tvB=0;
208 BOOL analog_on_A, analog_on_B;
209 ULONG oldhead;
210 UBYTE cr44;
211
212 if(implementation_masked != 0x0110) {
213 if(sd->Card.PRAMDAC0[0x0000052C/4] & 0x100)
214 outputAfromCRTC = 1;
215 else
216 outputAfromCRTC = 0;
217 if(sd->Card.PRAMDAC0[0x0000252C/4] & 0x100)
218 outputBfromCRTC = 1;
219 else
220 outputBfromCRTC = 0;
221 analog_on_A = NVIsConnected(sd, 0);
222 analog_on_B = NVIsConnected(sd, 1);
223 } else {
224 outputAfromCRTC = 0;
225 outputBfromCRTC = 1;
226 analog_on_A = FALSE;
227 analog_on_B = FALSE;
228 }
229
230 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
231 cr44 = VGA_RD08(sd->Card.PCIO, 0x03D5);
232
233 VGA_WR08(sd->Card.PCIO, 0x03D5, 3);
234 NVSelectHead(sd, 1);
235 NVLockUnlock(sd, 0);
236
237 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x28);
238 slaved_on_B = VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x80;
239 if(slaved_on_B) {
240 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x33);
241 tvB = !(VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x01);
242 }
243
244 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
245 VGA_WR08(sd->Card.PCIO, 0x03D5, 0);
246 NVSelectHead(sd, 0);
247 NVLockUnlock(sd, 0);
248
249 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x28);
250 slaved_on_A = VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x80;
251 if(slaved_on_A) {
252 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x33);
253 tvA = !(VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x01);
254 }
255
256 oldhead = sd->Card.PCRTC0[0x00000860/4];
257 sd->Card.PCRTC0[0x00000860/4] = oldhead | 0x00000010;
258
259 if(slaved_on_A && !tvA) {
260 CRTCnumber = 0;
261 sd->Card.FlatPanel = 1;
262 } else
263 if(slaved_on_B && !tvB) {
264 CRTCnumber = 1;
265 sd->Card.FlatPanel = 1;
266 } else
267 if(analog_on_A) {
268 CRTCnumber = outputAfromCRTC;
269 sd->Card.FlatPanel = 0;
270 } else
271 if(analog_on_B) {
272 CRTCnumber = outputBfromCRTC;
273 sd->Card.FlatPanel = 0;
274 } else
275 if(slaved_on_A) {
276 CRTCnumber = 0;
277 sd->Card.FlatPanel = 1;
278 sd->Card.Television = 1;
279 } else
280 if(slaved_on_B) {
281 CRTCnumber = 1;
282 sd->Card.FlatPanel = 1;
283 sd->Card.Television = 1;
284 }
285
286 if (CRTCnumber == -1)
287 {
288 D(bug("[NVidia] Unable to detect CRTC number, using defaults\n"));
289
290 if (sd->Card.FlatPanel) sd->Card.CRTCnumber = 1;
291 else sd->Card.CRTCnumber = 0;
292 }
293 else sd->Card.CRTCnumber = CRTCnumber;
294
295 if(implementation_masked == 0x0110)
296 cr44 = sd->Card.CRTCnumber * 0x3;
297
298 sd->Card.PCRTC0[0x00000860/4] = oldhead;
299
300 VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
301 VGA_WR08(sd->Card.PCIO, 0x03D5, cr44);
302 NVSelectHead(sd, sd->Card.CRTCnumber);
303 }
304
305 if (sd->Card.FlatPanel && !sd->Card.Television)
306 {
307 sd->Card.fpWidth = sd->Card.PRAMDAC[0x0820/4] + 1;
308 sd->Card.fpHeight= sd->Card.PRAMDAC[0x0800/4] + 1;
309 }
310
311 sd->Card.PRAMDAC[0x0300/4] = 0;
312
313 D(bug("[NVidia] Configuration received.\n"));
314 D(bug("[NVidia] Card has %dMB of video memory\n",
315 sd->Card.RamAmountKBytes >> 10));
316
317 sd->Card.FrameBufferSize = sd->Card.RamAmountKBytes * 1024;
318 sd->Card.FbUsableSize = sd->Card.FrameBufferSize - 128 * 1024;
319
320 D(bug("[NVidia] Max clock is %dMHz\n",
321 sd->Card.MaxVClockFreqKHz / 1000));
322
323 kprintf("\n=== NVidia GenericInit FlatPanel = %d TwoHeads = %d CRTCnumber = %d twostagepll = %d\n\n",
324 sd->Card.FlatPanel,
325 sd->Card.twoHeads,
326 sd->Card.CRTCnumber,
327 sd->Card.twoStagePLL);
328
329 return TRUE;
330 }
331
332 static BOOL NV4Init(struct staticdata *sd)
333 {
334 sd->Card.PRAMIN = sd->Card.Registers + 0x00710000;
335 sd->Card.PCRTC0 = sd->Card.Registers + 0x00600000;
336 return GenericInit(sd);
337 }
338
339 static BOOL NV10Init(struct staticdata *sd)
340 {
341 return NV4Init(sd);
342 }
343
344 static BOOL NV20Init(struct staticdata *sd)
345 {
346 return NV4Init(sd);
347 }
348
349 /* List of DeviceID's of supported nvidia cards */
350 static const struct NVDevice {
351 UWORD VendorID, ProductID;
352 CardType Type;
353 UWORD Arch;
354 BOOL (*Init)(struct staticdata*);
355 BOOL masked_check;
356
357 } support[] = {
358
359 /* Known: match ProductID exactly */
360 { 0x10de, 0x0020, NV04, NV_ARCH_04, NV4Init, FALSE }, /* RIVA TNT */
361 { 0x10de, 0x0028, NV05, NV_ARCH_04, NV4Init, FALSE }, /* RIVA TNT2 */
362 { 0x10de, 0x0029, NV05, NV_ARCH_04, NV4Init, FALSE }, /* RIVA TNT2 Ultra */
363 { 0x10de, 0x002a, NV05, NV_ARCH_04, NV4Init, FALSE }, /* Unknown TNT2 */
364 { 0x10de, 0x002b, NV05, NV_ARCH_04, NV4Init, FALSE },
365 { 0x10de, 0x002c, NV05, NV_ARCH_04, NV4Init, FALSE }, /* Vanta */
366 { 0x10de, 0x002d, NV05M64, NV_ARCH_04, NV4Init, FALSE }, /* RIVA TNT2 Model 64 */
367 { 0x10de, 0x002e, NV06, NV_ARCH_04, NV4Init, FALSE },
368 { 0x10de, 0x002f, NV06, NV_ARCH_04, NV4Init, FALSE },
369 { 0x10de, 0x00a0, NV05, NV_ARCH_04, NV4Init, FALSE }, /* Aladdin TNT2 */
370 { 0x10de, 0x0100, NV10, NV_ARCH_10, NV10Init, FALSE }, /* GeForce 256 */
371 { 0x10de, 0x0101, NV10, NV_ARCH_10, NV10Init, FALSE }, /* GeForce DDR */
372 { 0x10de, 0x0102, NV10, NV_ARCH_10, NV10Init, FALSE },
373 { 0x10de, 0x0103, NV10, NV_ARCH_10, NV10Init, FALSE }, /* Quadro */
374 { 0x10de, 0x0110, NV11, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 MX/MX 400 */
375 { 0x10de, 0x0111, NV11, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 MX 100/200 */
376 { 0x10de, 0x0112, NV11, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 Go */
377 { 0x10de, 0x0113, NV11, NV_ARCH_10, NV10Init, FALSE }, /* Quadro2 MXR/EX/Go */
378 { 0x10de, 0x0150, NV15, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 GTS */
379 { 0x10de, 0x0151, NV15, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 Ti */
380 { 0x10de, 0x0152, NV15, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 Ultra */
381 { 0x10de, 0x0153, NV15, NV_ARCH_10, NV10Init, FALSE }, /* Quadro2 Pro */
382 { 0x10de, 0x0170, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 460 */
383 { 0x10de, 0x0171, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 440 */
384 { 0x10de, 0x0172, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 420 */
385 { 0x10de, 0x0173, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 440-SE */
386 { 0x10de, 0x0174, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 440 Go */
387 { 0x10de, 0x0175, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 420 Go */
388 { 0x10de, 0x0176, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 420 Go 32M */
389 { 0x10de, 0x0177, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 460 Go */
390 { 0x10de, 0x0178, NV17, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 550 XGL */
391 { 0x10de, 0x0179, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 440 Go 64M / GeForce4 Mx (Mac) */
392 { 0x10de, 0x017a, NV17, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 NVS */
393 { 0x10de, 0x017c, NV17, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 500 GoGL */
394 { 0x10de, 0x017d, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 410 Go 16M */
395 { 0x10de, 0x0180, NV18, NV_ARCH_10, NV10Init, FALSE },
396 { 0x10de, 0x0181, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 440 with AGP8x */
397 { 0x10de, 0x0182, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 440SE with AGP8x */
398 { 0x10de, 0x0183, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX 420 with AGP8x */
399 { 0x10de, 0x0186, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 448 Go */
400 { 0x10de, 0x0187, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 488 Go */
401 { 0x10de, 0x0188, NV18, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 580 XGL */
402 { 0x10de, 0x0189, NV18, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX with AGP8X (Mac) */
403 { 0x10de, 0x018a, NV18, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 280 NVS */
404 { 0x10de, 0x018b, NV18, NV_ARCH_10, NV10Init, FALSE }, /* Quadro4 380 XGL */
405 { 0x10de, 0x01a0, NV11, NV_ARCH_10, NV10Init, FALSE }, /* GeForce2 Integrated GPU */
406 { 0x10de, 0x01f0, NV17, NV_ARCH_10, NV10Init, FALSE }, /* GeForce4 MX Integerated GPU */
407 { 0x10de, 0x0200, NV20, NV_ARCH_20, NV20Init, FALSE }, /* GeForce3 */
408 { 0x10de, 0x0201, NV20, NV_ARCH_20, NV20Init, FALSE }, /* GeForce3 Ti 200 */
409 { 0x10de, 0x0202, NV20, NV_ARCH_20, NV20Init, FALSE }, /* GeForce3 Ti 500 */
410 { 0x10de, 0x0203, NV20, NV_ARCH_20, NV20Init, FALSE }, /* Quadro DCC */
411 { 0x10de, 0x0250, NV25, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4600 */
412 { 0x10de, 0x0251, NV25, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4400 */
413 { 0x10de, 0x0252, NV25, NV_ARCH_20, NV20Init, FALSE }, /* 0x252 */
414 { 0x10de, 0x0253, NV25, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4200 */
415 { 0x10de, 0x0258, NV25, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 900 XGL */
416 { 0x10de, 0x0259, NV25, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 750 XGL */
417 { 0x10de, 0x025b, NV25, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 700 XGL */
418 { 0x10de, 0x0280, NV28, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4800 */
419 { 0x10de, 0x0281, NV28, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4200 with AGP8X */
420 { 0x10de, 0x0282, NV28, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 Ti 4800 SE */
421 { 0x10de, 0x0286, NV28, NV_ARCH_20, NV20Init, FALSE }, /* GeForce4 4200 Go */
422 { 0x10de, 0x0288, NV28, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 980 XGL */
423 { 0x10de, 0x0289, NV28, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 780 XGL */
424 { 0x10de, 0x028c, NV28, NV_ARCH_20, NV20Init, FALSE }, /* Quadro4 700 GoGL */
425 { 0x10de, 0x02a0, NV20, NV_ARCH_20, NV20Init, FALSE },
426 { 0x10de, 0x0301, NV30, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5800 Ultra */
427 { 0x10de, 0x0302, NV30, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5800 */
428 { 0x10de, 0x0308, NV30, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 2000 */
429 { 0x10de, 0x0309, NV30, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 1000 */
430 { 0x10de, 0x0311, NV31, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5600 Ultra */
431 { 0x10de, 0x0312, NV31, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5600 */
432 { 0x10de, 0x0313, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x313 */
433 { 0x10de, 0x0314, NV31, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5600 SE */
434 { 0x10de, 0x0316, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x316 */
435 { 0x10de, 0x0317, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x317 */
436 { 0x10de, 0x031a, NV31, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5600 */
437 { 0x10de, 0x031b, NV31, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5650 */
438 { 0x10de, 0x031c, NV31, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX Go700 */
439 { 0x10de, 0x031d, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x31d */
440 { 0x10de, 0x031e, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x31e */
441 { 0x10de, 0x031f, NV31, NV_ARCH_30, NV20Init, FALSE }, /* 0x31f */
442 { 0x10de, 0x0320, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5200 */
443 { 0x10de, 0x0321, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5200 Ultra */
444 { 0x10de, 0x0322, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5200 */
445 { 0x10de, 0x0323, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5200SE */
446 { 0x10de, 0x0324, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5200 */
447 { 0x10de, 0x0325, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5250 */
448 { 0x10de, 0x0326, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5500 */
449 { 0x10de, 0x0327, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5100 */
450 { 0x10de, 0x0328, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5200 32M/64M */
451 { 0x10de, 0x0329, NV34, NV_ARCH_30, NV20Init, FALSE }, /* 0x329 / GeForce FX 5200 (Mac) */
452 { 0x10de, 0x032a, NV34, NV_ARCH_30, NV20Init, FALSE }, /* Quadro NVS 280 PCI */
453 { 0x10de, 0x032b, NV34, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 500/600 PCI */
454 { 0x10de, 0x032c, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go53xx Series */
455 { 0x10de, 0x032d, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5100 */
456 { 0x10de, 0x032e, NV34, NV_ARCH_30, NV20Init, FALSE },
457 { 0x10de, 0x032f, NV34, NV_ARCH_30, NV20Init, FALSE }, /* 0x32F */
458 { 0x10de, 0x0330, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce Fx 5900 Ultra */
459 { 0x10de, 0x0331, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5900 */
460 { 0x10de, 0x0332, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5900XT */
461 { 0x10de, 0x0333, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5950 Ultra */
462 { 0x10de, 0x0334, NV34, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5900ZT */
463 { 0x10de, 0x0338, NV34, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 3000 */
464 { 0x10de, 0x033F, NV34, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 700 */
465 { 0x10de, 0x0341, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5700 Ultra */
466 { 0x10de, 0x0342, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5700 */
467 { 0x10de, 0x0343, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5700LE */
468 { 0x10de, 0x0344, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX 5700VE */
469 { 0x10de, 0x0345, NV36, NV_ARCH_30, NV20Init, FALSE }, /* 0x345 */
470 { 0x10de, 0x0347, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5700 */
471 { 0x10de, 0x0348, NV36, NV_ARCH_30, NV20Init, FALSE }, /* GeForce FX Go5700 */
472 { 0x10de, 0x0349, NV36, NV_ARCH_30, NV20Init, FALSE }, /* 0x349 */
473 { 0x10de, 0x034B, NV36, NV_ARCH_30, NV20Init, FALSE }, /* 0x34B */
474 { 0x10de, 0x034C, NV36, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX Go1000 */
475 { 0x10de, 0x034E, NV36, NV_ARCH_30, NV20Init, FALSE }, /* Quadro FX 1100 */
476 { 0x10de, 0x034F, NV36, NV_ARCH_30, NV20Init, FALSE }, /* 0x34F */
477 { 0x10de, 0x0040, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6800 Ultra */
478 { 0x10de, 0x0041, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6800 */
479 { 0x10de, 0x0042, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6800 LE */
480 { 0x10de, 0x0043, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x043 */
481 { 0x10de, 0x0045, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6800 GT */
482 { 0x10de, 0x0049, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x049 */
483 { 0x10de, 0x004E, NV36, NV_ARCH_40, NV20Init, FALSE }, /* Quadro FX 4000 */
484 { 0x10de, 0x00C0, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0C0 */
485 { 0x10de, 0x00C1, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0C1 */
486 { 0x10de, 0x00C2, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0C2 */
487 { 0x10de, 0x00C8, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0C8 */
488 { 0x10de, 0x00C9, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0C9 */
489 { 0x10de, 0x00CC, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0CC */
490 { 0x10de, 0x00CE, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0CE */
491 { 0x10de, 0x00F1, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6600 / GeForce 6600 GT (Verified: LeadTek GeForce 6600 GT) */
492 { 0x10de, 0x00F2, NV43, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6600 / GeForce 6600 GT (Verified: Club3D GeForce 6600) */
493 { 0x10de, 0x0140, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6600 GT */
494 { 0x10de, 0x0141, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6600 */
495 { 0x10de, 0x0142, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0142 */
496 { 0x10de, 0x0143, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0143 */
497 { 0x10de, 0x0144, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0144 */
498 { 0x10de, 0x0145, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6610 XL */
499 { 0x10de, 0x0146, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0146 */
500 { 0x10de, 0x0147, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0147 */
501 { 0x10de, 0x0148, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0148 */
502 { 0x10de, 0x0149, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0149 */
503 { 0x10de, 0x014B, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x014B */
504 { 0x10de, 0x014C, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x014C */
505 { 0x10de, 0x014D, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x014D */
506 { 0x10de, 0x014E, NV36, NV_ARCH_40, NV20Init, FALSE }, /* Quadro FX 540 */
507 { 0x10de, 0x014F, NV36, NV_ARCH_40, NV20Init, FALSE }, /* GeForce 6200 */
508 { 0x10de, 0x0160, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0160 */
509 { 0x10de, 0x0166, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0166 */
510 { 0x10de, 0x0210, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0210 */
511 { 0x10de, 0x0211, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x0211 */
512 { 0x10de, 0x021D, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x021D */
513 { 0x10de, 0x021E, NV36, NV_ARCH_40, NV20Init, FALSE }, /* 0x021E */
514
515 /* Unknown: Match ProductID & 0xFFF0 */
516 { 0x10de, 0x0170, NV17, NV_ARCH_10, NV10Init, TRUE },
517 { 0x10de, 0x0180, NV18, NV_ARCH_10, NV10Init, TRUE },
518 { 0x10de, 0x0250, NV25, NV_ARCH_20, NV20Init, TRUE },
519 { 0x10de, 0x0280, NV28, NV_ARCH_20, NV20Init, TRUE },
520 { 0x10de, 0x0300, NV30, NV_ARCH_30, NV20Init, TRUE },
521 { 0x10de, 0x0310, NV31, NV_ARCH_30, NV20Init, TRUE },
522 { 0x10de, 0x0320, NV34, NV_ARCH_30, NV20Init, TRUE },
523 { 0x10de, 0x0340, NV34, NV_ARCH_30, NV20Init, TRUE },
524 { 0x10de, 0x0040, NV36, NV_ARCH_40, NV20Init, TRUE },
525 { 0x10de, 0x00C0, NV36, NV_ARCH_40, NV20Init, TRUE },
526 { 0x10de, 0x0120, NV36, NV_ARCH_40, NV20Init, TRUE },
527 { 0x10de, 0x0140, NV36, NV_ARCH_40, NV20Init, TRUE },
528 { 0x10de, 0x0160, NV36, NV_ARCH_40, NV20Init, TRUE },
529 { 0x10de, 0x0130, NV36, NV_ARCH_40, NV20Init, TRUE },
530 { 0x10de, 0x01D0, NV36, NV_ARCH_40, NV20Init, TRUE },
531 { 0x10de, 0x0090, NV36, NV_ARCH_40, NV20Init, TRUE },
532 { 0x10de, 0x0210, NV36, NV_ARCH_40, NV20Init, TRUE },
533
534 { 0x0000, 0x0000, }
535 };
536
537 #define sd ((struct staticdata*)hook->h_Data)
538 AROS_UFH3(void, Enumerator,
539 AROS_UFHA(struct Hook *, hook, A0),
540 AROS_UFHA(OOP_Object *, pciDevice, A2),
541 AROS_UFHA(APTR, message, A1))
542 {
543 AROS_USERFUNC_INIT
544
545 struct NVDevice *sup = (struct NVDevice *)support;
546 IPTR ProductID;
547 IPTR VendorID;
548
549 /* Get the Device's ProductID */
550 OOP_GetAttr(pciDevice, aHidd_PCIDevice_ProductID, &ProductID);
551 OOP_GetAttr(pciDevice, aHidd_PCIDevice_VendorID, &VendorID);
552
553 D(bug("[NVidia] Enumerator: checking productid %d vendorid %d sd->Deivce %x\n",
554 ProductID, VendorID, sd->Device));
555
556 /* And try to match it with supported cards */
557 while (sup->VendorID)
558 {
559 BOOL found = FALSE;
560
561 if (sup->VendorID == VendorID)
562 {
563 if (!sup->masked_check && (sup->ProductID == ProductID))
564 {
565 found = TRUE;
566 }
567 else if (sup->masked_check && (sup->ProductID == (ProductID & 0xFFF0)))
568 {
569 found = TRUE;
570 }
571 }
572
573 if (found)
574 {
575 /* Matching card found */
576 APTR buf;
577 IPTR size;
578 struct pHidd_PCIDriver_MapPCI mappci,*msg = &mappci;
579 OOP_Object *driver;
580 struct MemChunk *mc;
581
582 struct TagItem attrs[] = {
583 { aHidd_PCIDevice_isIO, FALSE }, /* Don't listen IO transactions */
584 { aHidd_PCIDevice_isMEM, TRUE }, /* Listen to MEM transactions */
585 { aHidd_PCIDevice_isMaster, TRUE }, /* Can work in BusMaster */
586 { TAG_DONE, 0UL },
587 };
588
589 D(bug("[NVidia] Enumerator: found productid %d vendorid %d masked_check %d\n",
590 sup->ProductID, sup->VendorID, sup->masked_check));
591
592
593 sd->Card.ProductID = ProductID;
594 sd->Card.VendorID = VendorID;
595 sd->Card.Type = sup->Type;
596 sd->Card.Architecture = sup->Arch;
597 sd->Card.Chipset = ProductID;
598
599 D(bug("[NVidia] Chip architecture = %d\n", sd->Card.Architecture));
600
601 /*-------- DO NOT CHANGE/REMOVE -------------*/
602 bug("\003\n"); /* Tell vga text mode debug output to die */
603 /*-------- DO NOT CHANGE/REMOVE -------------*/
604
605 /*
606 Fix PCI device attributes (perhaps already set, but if the
607 NVidia would be the second card in the system, it may stay
608 uninitialized.
609 */
610 OOP_SetAttrs(pciDevice, (struct TagItem*)&attrs);
611
612 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Driver, (APTR)&driver);
613 sd->pcidriver = driver;
614
615 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base1, (APTR)&buf);
616 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size1, (APTR)&size);
617
618 sd->mid_ReadLong = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_ReadConfigLong);
619
620 mappci.mID = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_MapPCI);
621 mappci.PCIAddress = buf;
622 mappci.Length = size;
623
624 sd->Card.FbAddress = buf;
625 sd->Card.FrameBuffer = (APTR)OOP_DoMethod(driver, (OOP_Msg)msg);
626 mc = (struct MemChunk *)sd->Card.FrameBuffer;
627
628 sd->CardMem->mh_Node.ln_Type = NT_MEMORY;
629 sd->CardMem->mh_Node.ln_Name = "nVidia Framebuffer";
630 sd->CardMem->mh_First = mc;
631 sd->CardMem->mh_Lower = (APTR)mc;
632
633 D(bug("[NVidia] Got framebuffer @ %x (size=%x)\n", sd->Card.FrameBuffer, size));
634
635 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base0, (APTR)&buf);
636 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size0, (APTR)&size);
637
638 mappci.PCIAddress = buf;
639 mappci.Length = size;
640
641 sd->Card.Registers = (APTR)OOP_DoMethod(driver, (OOP_Msg)msg);
642 D(bug("[NVidia] Got registers @ %x (size=%x)\n", sd->Card.Registers, size));
643
644 if (sup->Init(sd))
645 {
646 struct CardState *state = (struct CardState *)AllocPooled(sd->memPool,
647 sizeof(struct CardState));
648
649 sd->CardMem->mh_Free = sd->Card.FbUsableSize;
650 sd->CardMem->mh_Upper = (APTR)(sd->CardMem->mh_Free + (IPTR)mc);
651
652 mc->mc_Next = NULL;
653 mc->mc_Bytes = sd->CardMem->mh_Free;
654
655 D(bug("[NVidia] Usable size: %dKB\n", sd->CardMem->mh_Free >> 10));
656
657 sd->Device = pciDevice;
658
659 InitMode(sd, state, 640, 480, 16, 25200, 0,
660 640, 480,
661 656, 752, 800,
662 490, 492, 525);
663 /*
664 InitMode(sd, state, 800, 600, 24, 36000, 0,
665 800, 600,
666 824, 896, 1024,
667 601, 603, 625);
668 */
669 LoadState(sd, state);
670 DPMS(sd,vHidd_Gfx_DPMSLevel_On);
671
672 sd->scratch_buffer = AllocBitmapArea(sd, 65536, 1, 4, TRUE);
673 // acc_test(sd);
674 }
675 else
676 {
677 struct pHidd_PCIDriver_UnmapPCI unmappci,*msg=&unmappci;
678
679 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size1, (APTR)&size);
680
681 unmappci.mID = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_UnmapPCI);
682 unmappci.CPUAddress = sd->Card.FrameBuffer;
683 unmappci.Length = size;
684
685 OOP_DoMethod(driver, (OOP_Msg)msg);
686
687 OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size0, (APTR)&size);
688 unmappci.CPUAddress = sd->Card.Registers;
689 unmappci.Length = size;
690
691 OOP_DoMethod(driver, (OOP_Msg)msg);
692
693 sd->Device = NULL;
694 }
695
696 break;
697 }
698 sup++;
699 }
700
701 D(bug("[NVidia] Enumerator found a card (ProductID=%04x)\n", ProductID));
702 D(bug("[NVidia] The card is %ssupported\n",
703 sd->Device ? "":"un"));
704
705 AROS_USERFUNC_EXIT
706 }
707
708 #undef sd
709 static void Find_NV_Card(struct staticdata *sd)
710 {
711 D(bug("[NVidia] Find_NV_Card\n"));
712
713 if (HiddPCIDeviceAttrBase)
714 {
715 sd->pci = OOP_NewObject(NULL, CLID_Hidd_PCI, NULL);
716
717 D(bug("[NVidia] Creating PCI object\n"));
718
719 if (sd->pci)
720 {
721 struct Hook FindHook = {
722 h_Entry: (IPTR (*)())Enumerator,
723 h_Data: sd,
724 };
725
726 struct TagItem Requirements[] = {
727 { tHidd_PCI_Interface, 0x00 },
728 { tHidd_PCI_Class, 0x03 },
729 { tHidd_PCI_SubClass, 0x00 },
730 { tHidd_PCI_VendorID, 0x10de }, // NVidia VendorID. May require more of them
731 { TAG_DONE, 0UL }
732 };
733
734 struct pHidd_PCI_EnumDevices enummsg = {
735 mID: OOP_GetMethodID(IID_Hidd_PCI, moHidd_PCI_EnumDevices),
736 callback: &FindHook,
737 requirements: (struct TagItem*)&Requirements,
738 }, *msg = &enummsg;
739 D(bug("[NVidia] Calling search Hook\n"));
740 OOP_DoMethod(sd->pci, (OOP_Msg)msg);
741 }
742 }
743 }
744
745 static int NV_Init(LIBBASETYPEPTR LIBBASE)
746 {
747 D(bug("[NVidia] Initialization\n"));
748
749 /* Global memory pool and static data creation */
750 LIBBASE->memPool = CreatePool(MEMF_CLEAR | MEMF_PUBLIC | MEMF_SEM_PROTECTED, 8192, 4096);
751 if (LIBBASE->memPool)
752 {
753 struct staticdata *sd = &LIBBASE->sd;
754
755 sd->memPool = LIBBASE->memPool;
756 sd->CardMem = &LIBBASE->mh;
757
758 InitSemaphore(&sd->HWLock);
759 InitSemaphore(&sd->MultiBMLock);
760
761 sd->dpms = vHidd_Gfx_DPMSLevel_On;
762
763 {
764 struct OOP_ABDescr attrbases[] =
765 {
766 { IID_Hidd_PCIDevice, &HiddPCIDeviceAttrBase },
767 { IID_Hidd_BitMap, &HiddBitMapAttrBase },
768 { IID_Hidd_PixFmt, &HiddPixFmtAttrBase },
769 { IID_Hidd_Sync, &HiddSyncAttrBase },
770 { IID_Hidd_Gfx, &HiddGfxAttrBase },
771 { IID_Hidd_nvBitMap, &HiddNVidiaBitMapAttrBase },
772 { IID_Hidd_PlanarBM, &__IHidd_PlanarBM },
773 { NULL, NULL }
774 };
775
776 sd->basebm = OOP_FindClass(CLID_Hidd_BitMap);
777
778 if (OOP_ObtainAttrBases(attrbases))
779 {
780 Find_NV_Card(sd);
781
782 if (sd->Device != NULL)
783 return TRUE;
784 }
785
786 OOP_ReleaseAttrBases(attrbases);
787
788 OOP_DisposeObject(sd->pci);
789 }
790 }
791
792 /*
793 Something failed. Ehm, that shouldn't happen at all. Now we have to
794 clean everything up
795 */
796 DeletePool(LIBBASE->memPool);
797
798 D(bug("[NVidia] nvBase=%x. FAILURE! Now freezing so you can check debug output!\n", LIBBASE));
799
800 Disable(); for(;;) ;
801
802 return FALSE;
803 }
804
805 ADD2INITLIB(NV_Init, 0)
Mirror of AROS' svn.