arch/arm-native/kernel/mmu.c

   1 /*
   2     Copyright � 2013, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <inttypes.h>
   7 #include <aros/kernel.h>
   8 #include <aros/libcall.h>
   9 #include <asm/arm/mmu.h>
  10 #include <stddef.h>
  11 #include <string.h>
  12
  13 #include <proto/exec.h>
  14 #include <proto/kernel.h>
  15
  16 #include "kernel_intern.h"
  17 #include "mmu.h"
  18
  19 unsigned int pagetable[4096]    __attribute__ ((aligned (16384)));
  20 unsigned int pagetable0[64]     __attribute__ ((aligned (16384)));
  21
  22 void core_MMUUpdatePageTables(void)
  23 {
  24     unsigned int pt_addr = (unsigned int) &pagetable;
  25     unsigned int pt0_addr = (unsigned int) &pagetable0;
  26
  27     /* Invalidate caches */
  28     asm volatile("mcr   p15, 0, %[r], c8, c7, 0" : : [r] "r" (0x0));   //Invalidate entire unified TLB
  29     asm volatile("mcr   p15, 0, %[r], c8, c6, 0" : : [r] "r" (0x0));   //Invalidate entire data TLB
  30     asm volatile("mcr   p15, 0, %[r], c8, c5, 0" : : [r] "r" (0x0));   //Invalidate entire instruction TLB
  31     asm volatile("mcr   p15, 0, %[r], c7, c5, 6" : : [r] "r" (0x0));   //Invalidate entire branch prediction array
  32     asm volatile("mcr   p15, 0, %[r], c7, c5, 0" : : [r] "r" (0x0));   //Invalidate icache
  33
  34     /* setup_ttbr0/1 */
  35     asm volatile("mcr   p15, 0, %[addr], c2, c0, 0" : : [addr] "r" (pt0_addr));
  36     asm volatile("mcr   p15, 0, %[addr], c2, c0, 1" : : [addr] "r" (pt_addr));
  37     /* setup_ttbrc */
  38     asm volatile("mcr   p15, 0, %[n], c2, c0, 2" : : [n] "r" (7));
  39 }
  40
  41 void core_SetupMMU(struct TagItem *msg)
  42 {
  43     unsigned int page;
  44     register unsigned int control;
  45
  46     D(bug("[Kernel] core_SetupMMU: Creating MMU pagetable[0] entries for 4GB address space\n"));
  47
  48     for (page = 0; page < 4096; page ++)
  49     {
  50         unsigned int pageflags = PAGE_TRANSLATIONFAULT;
  51         if (page > 64)
  52         {
  53             pageflags = (page << 20) | PAGE_FL_S_BIT | PAGE_SECTION;
  54 #if defined(ARM_PERIIOBASE)
  55             if ((page < (ARM_PERIIOBASE >> 20)) || (page > ((ARM_PERIIOBASE + ARM_PERIIOSIZE) >> 20)))
  56 #endif
  57                 pageflags |= PAGE_C_BIT | PAGE_B_BIT | (1 << PAGE_TEX_SHIFT);
  58         }
  59         pagetable[page] = pageflags;
  60     }
  61
  62     D(bug("[Kernel] core_SetupMMU: Creating MMU pagetable[1] entries for 64MB address space\n"));
  63     for (page = 0; page < 64; page++)
  64     {
  65             pagetable0[page] = (page << 20) | PAGE_FL_S_BIT | PAGE_C_BIT | PAGE_SECTION | PAGE_B_BIT | (1 << PAGE_TEX_SHIFT);
  66     }
  67
  68     core_MMUUpdatePageTables();
  69
  70     /* Set the domain access control to all-supervisor */
  71     asm volatile("mcr   p15, 0, %[r], c3, c0, 0" : : [r] "r" (~0));
  72
  73     /* Enable L1 caches (I-cache and D-cache) and MMU.*/
  74     asm volatile("mrc   p15, 0, %[control], c1, c0, 0" : [control] "=r" (control));
  75     control |= ( ENABLE_I_CACHE | ENABLE_D_CACHE | ENABLE_MMU );
  76     asm volatile ("mcr  p15, 0, %[r], c7, c10, 4" : : [r] "r" (0)); /* dsb */
  77     asm volatile ("mcr  p15, 0, %0, c1, c0, 0" : : "r" (control) : "cc" );
  78     asm volatile ("mcr  p15, 0, %[r], c7, c5, 4" : : [r] "r" (0)); /* isb */
  79
  80     D(bug("[Kernel] core_SetupMMU: Done\n"));
  81 }
  82
  83 void core_ProtPage(intptr_t addr, char p, char rw, char us)
  84 {
  85     D(bug("[Kernel] Marking page 0x%p as read-only\n", addr));
  86
  87     core_MMUUpdatePageTables();
  88 }
  89
  90 void core_ProtKernelArea(intptr_t addr, intptr_t length, char p, char rw, char us)
  91 {
  92     D(bug("[Kernel] Protecting area 0x%p - 0x%p\n", addr, addr + length - 1));
  93     while (length > 0)
  94     {
  95         core_ProtPage(addr, p, rw, us);
  96         addr += 4096;
  97         length -= 4096;
  98     }
  99 }