2 Copyright � 2013-2015, The AROS Development Team. All rights reserved.
8 #include <aros/debug.h>
9 #include <aros/symbolsets.h>
10 #include <aros/libcall.h>
11 #include <proto/kernel.h>
12 #include <proto/exec.h>
13 #include <proto/mbox.h>
15 #include <hardware/bcm2708.h>
16 #include <hardware/videocore.h>
18 #include "mbox_private.h"
21 static int mbox_init(struct MBoxBase
*MBoxBase
)
25 D(bug("[MBox] mbox_init()\n"));
27 InitSemaphore(&MBoxBase
->mbox_Sem
);
29 D(bug("[MBox] mbox_init: Initialised Semaphore @ 0x%p\n", &MBoxBase
->mbox_Sem
));
34 AROS_LH1(unsigned int, MBoxStatus
,
35 AROS_LHA(void *, mb
, A0
),
36 struct MBoxBase
*, MBoxBase
, 1, Mbox
)
40 D(bug("[MBox] MBoxStatus(0x%p)\n", mb
));
42 return *((volatile unsigned int *)(mb
+ VCMB_STATUS
));
47 AROS_LH2(volatile unsigned int *, MBoxRead
,
48 AROS_LHA(void *, mb
, A0
),
49 AROS_LHA( unsigned int, chan
, D0
),
50 struct MBoxBase
*, MBoxBase
, 2, Mbox
)
54 unsigned int try = 0x2000000;
57 D(bug("[MBox] MBoxRead(chan %d @ 0x%p)\n", chan
, mb
));
59 if (chan
<= VCMB_CHAN_MAX
)
63 ObtainSemaphore(&MBoxBase
->mbox_Sem
);
64 APTR ssp
= SuperState();
65 while ((MBoxStatus(mb
) & VCMB_STATUS_READREADY
) != 0)
67 /* Data synchronization barrier */
68 asm volatile ("mcr p15, 0, %[r], c7, c10, 4" : : [r
] "r" (0) );
75 asm volatile ("mcr p15, 0, %[r], c7, c10, 5" : : [r
] "r" (0) );
77 msg
= *((volatile unsigned int *)(mb
+ VCMB_READ
));
79 asm volatile ("mcr p15, 0, %[r], c7, c10, 5" : : [r
] "r" (0) );
81 ReleaseSemaphore(&MBoxBase
->mbox_Sem
);
83 if ((msg
& VCMB_CHAN_MASK
) == chan
)
84 return (volatile unsigned int *)(msg
& ~VCMB_CHAN_MASK
);
87 return (volatile unsigned int *)-1;
92 AROS_LH3(void, MBoxWrite
,
93 AROS_LHA(void *, mb
, A0
),
94 AROS_LHA( unsigned int, chan
, D0
),
95 AROS_LHA(void *, msg
, A1
),
96 struct MBoxBase
*, MBoxBase
, 3, Mbox
)
100 D(bug("[MBOX] MBoxWrite(chan %d @ 0x%p, msg @ 0x%p)\n", chan
, mb
, msg
));
102 if ((((unsigned int)msg
& VCMB_CHAN_MASK
) == 0) && (chan
<= VCMB_CHAN_MAX
))
104 ObtainSemaphore(&MBoxBase
->mbox_Sem
);
105 APTR ssp
= SuperState();
106 while ((MBoxStatus(mb
) & VCMB_STATUS_WRITEREADY
) != 0)
108 /* Data synchronization barrier */
109 asm volatile ("mcr p15, 0, %[r], c7, c10, 4" : : [r
] "r" (0) );
112 asm volatile ("mcr p15, 0, %[r], c7, c10, 5" : : [r
] "r" (0) );
114 *((volatile unsigned int *)(mb
+ VCMB_WRITE
)) = ((unsigned int)msg
| chan
);
116 ReleaseSemaphore(&MBoxBase
->mbox_Sem
);
122 ADD2INITLIB(mbox_init
, 0)