arch/arm-raspi/boot/mmu.c

   1 /*
   2     Copyright © 2013-2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: mmu.c
   6     Lang: english
   7  */
   8
   9 #include <stdint.h>
  10 #include <hardware/bcm2708_boot.h>
  11 #include "mmu.h"
  12 #include "boot.h"
  13
  14 #define DMMU(x) x
  15
  16 void mmu_init()
  17 {
  18     static pde_t *pde = BOOTMEMADDR(bm_pde);
  19     int i;
  20
  21     for (i = 0; i < 4096; i++)
  22     {
  23 #if 0
  24         pde[i].raw = i << 20;
  25         pde[i].section.type = PDE_TYPE_SECTION;
  26         pde[i].section.b = 1;
  27         pde[i].section.c = 1;
  28         pde[i].section.ap = 3;
  29         pde[i].section.apx = 0;
  30         pde[i].section.tex = 1;
  31 #else
  32         pde[i].raw = 0;
  33 #endif
  34     }
  35 }
  36
  37 void mmu_load()
  38 {
  39     uint32_t tmp;
  40
  41     static pde_t *pde = BOOTMEMADDR(bm_pde);
  42
  43     arm_flush_cache((uint32_t)pde, 16384);
  44
  45     /* Write page_dir address to ttbr0 */
  46     asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(pde));
  47     /* Write ttbr control N = 0 (use only ttbr0) */
  48     asm volatile ("mcr p15, 0, %0, c2, c0, 2"::"r"(0));
  49
  50     /* Set domains - Dom0 is usable, rest is disabled */
  51     asm volatile ("mrc p15, 0, %0, c3, c0, 0":"=r"(tmp));
  52     DMMU(kprintf("[BOOT] Domain access control register: %08x\n", tmp));
  53     asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(0x00000001));
  54
  55     asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r"(tmp));
  56     DMMU(kprintf("[BOOT] control register %08x\n", tmp));
  57     tmp |= 1;           /* Enable MMU */
  58     tmp |= 1 << 23;     /* v6 page tables, subpages disabled */
  59     asm volatile ("mcr  p15, 0, %[r], c7, c10, 4" : : [r] "r" (0)); /* dsb */
  60     asm volatile ("mcr p15, 0, %0, c1, c0, 0"::"r"(tmp));
  61     asm volatile ("mcr  p15, 0, %[r], c7, c5, 4" : : [r] "r" (0)); /* isb */
  62 }
  63
  64 void mmu_unmap_section(uint32_t virt, uint32_t length)
  65 {
  66     static pde_t *pde = BOOTMEMADDR(bm_pde);
  67
  68     uint32_t start = virt & ~(1024*1024-1);
  69     uint32_t end = (start + length) & ~(1024*1024-1);
  70
  71     start >>= 20;
  72     end >>= 20;
  73
  74     while (start < end)
  75     {
  76         pde[start].raw = 0;
  77         start++;
  78     }
  79 }
  80
  81 void mmu_map_section(uint32_t phys, uint32_t virt, uint32_t length, int b, int c, int ap, int tex)
  82 {
  83     static pde_t *pde = BOOTMEMADDR(bm_pde);
  84
  85     uint32_t start = virt & ~(1024*1024-1);
  86     uint32_t end = (start + length) & ~(1024*1024-1);
  87
  88     DMMU(kprintf("[BOOT] MMU map %p:%p->%p:%p, b=%d, c=%d, ap=%x, tex=%x\n",
  89             phys, phys+length-1, virt, virt+length-1, b, c, ap, tex));
  90
  91     int count = (end - start) >> 20;
  92     int i = start >> 20;
  93     phys >>= 20;
  94
  95     while(count--)
  96     {
  97         pde_t s;
  98
  99         s.section.type = PDE_TYPE_SECTION;
 100         s.section.b = b;
 101         s.section.c = c;
 102         s.section.ap = ap & 3;
 103         s.section.apx = (ap >> 2) & 1;
 104         s.section.tex = tex;
 105         s.section.base_address = phys;
 106
 107         pde[i] = s;
 108
 109         phys++;
 110         i++;
 111     }
 112 }