arch/all-pc/kernel/apic_ia32.h

   1 /*
   2     Copyright © 1995-2011, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: IA-32 APIC hardware definitions.
   6     Lang: english
   7 */
   8
   9 /* Local APIC base address register (MSR #27) */
  10 #define MSR_LAPIC_BASE 0x1B
  11
  12 #define APIC_BOOTSTRAP (1 << 8)
  13 #define APIC_ENABLE    (1 << 11)
  14
  15 /* APIC hardware registers */
  16
  17 #define APIC_ID          0x20
  18 #define APIC_VERSION     0x30
  19 #define APIC_TPR         0x80   /* Task Priority Register                       */
  20 #define APIC_APR         0x90   /* Arbitration Priority Register                */
  21 #define APIC_PPR         0xA0   /* Processor Priority Register                  */
  22 #define APIC_EOI         0xB0   /* End Of Interrupt Register                    */
  23 #define APIC_REMOTE_READ 0xC0
  24 #define APIC_LDR         0xD0   /* Logical Destination Register                 */
  25 #define APIC_DFR         0xE0   /* Destination Format Register                  */
  26 #define APIC_SVR         0xF0   /* Spurious Interrupt Vector Register           */
  27 #define APIC_ISR         0x100  /* In Service Register                          */
  28 #define APIC_TMR         0x180  /* Trigger Mode Register                        */
  29 #define APIC_IRR         0x200  /* Interrupt Request Register                   */
  30 #define APIC_ESR         0x280  /* Error Status Register                        */
  31 #define APIC_ICRL        0x300  /* Interrupt Command Register low part          */
  32 #define APIC_ICRH        0x310  /* Interrupt Command Register high part         */
  33 #define APIC_TIMER_VEC   0x320  /* Timer local vector table entry               */
  34 #define APIC_THERMAL_VEC 0x330  /* Thermal local vector table entry             */
  35 #define APIC_PCOUNT_VEC  0x340  /* Performance counter local vector table entry */
  36 #define APIC_LINT0_VEC   0x350  /* Local interrupt 0 vector table entry         */
  37 #define APIC_LINT1_VEC   0x360  /* Local interrupt 1 vector table entry         */
  38 #define APIC_ERROR_VEC   0x370  /* Error vector table entry                     */
  39 #define APIC_TIMER_ICR   0x380  /* Timer initial count                          */
  40 #define APIC_TIMER_CCR   0x390  /* Timer current count                          */
  41 #define APIC_TIMER_DIV   0x3E0  /* Timer divide configuration register          */
  42
  43 /* ID shift value */
  44 #define APIC_ID_SHIFT 24
  45
  46 /* Version register */
  47 #define APIC_VERSION_MASK 0x000000FF    /* The actual version number                         */
  48 #define APIC_LVT_MASK     0x00FF0000    /* Number of entries in local vector table minus one */
  49 #define APIC_LVT_SHIFT    16
  50 #define APIC_EAS          (1 << 31)     /* Whether this APIC has extended address space      */
  51
  52 /* Macros to help parsing version */
  53 #define APIC_INTEGRATED(ver) (ver & 0x000000F0)
  54 #define APIC_LVT(ver)        ((ver & APIC_LVT_MASK) >> APIC_LVT_SHIFT)
  55
  56 /* LDR shift value */
  57 #define LDR_ID_SHIFT 24
  58
  59 /* Destination format (interrupt model) */
  60 #define DFR_CLUSTER (0x0 << 28)
  61 #define DFR_FLAT    (0xF << 28)
  62
  63 #define SVR_VEC_MASK 0xFF
  64 #define SVR_ASE      (1 << 8)
  65 #define SVR_FCC      (1 << 9)
  66
  67 /* Error register */
  68 #define ERR_SAE (1 << 2) /* Sent accept error        */
  69 #define ERR_RAE (1 << 3) /* Receive accept error     */
  70 #define ERR_SIV (1 << 5) /* Sent illegal vector      */
  71 #define ERR_RIV (1 << 6) /* Received illegal vector  */
  72 #define ERR_IRA (1 << 7) /* Illegal register address */
  73
  74 /* ICRL register */
  75 #define ICR_VEC_MASK      0x000000FF    /* Vector number (request argument) mask        */
  76 #define ICR_DM_INIT       0x0500        /* INIT request (reset the CPU)                 */
  77 #define ICR_DM_STARTUP    0x0600        /* STARTUP request (run from specified address) */
  78 #define ICR_DS            0x1000        /* Delivery status flag                         */
  79 #define ICR_INT_LEVELTRIG 0x8000        /* Send level-triggered interrupt               */
  80 #define ICR_INT_ASSERT    0x4000        /* Assert (set) or deassert (reset)             */
  81
  82 /* Local vector table entry fields */
  83 #define LVT_VEC_MASK   0x0000FF         /* Vector no                            */
  84 #define LVT_MT_MASK    0x000700         /* Message type                         */
  85 #define LVT_MT_FIXED   0x000000
  86 #define LVT_MT_SMI     0x000200
  87 #define LVT_MT_NMI     0x000400
  88 #define LVT_MT_EXT     0x000700
  89 #define LVT_DS         0x001000         /* Delivery status bit                  */
  90 #define LVT_ACTIVE_LOW 0x002000         /* Polarity flag (1 = low active)       */
  91 #define LVT_RIR        0x004000         /* Remote IRR                           */
  92 #define LVT_TGM_LEVEL  0x008000         /* Level-trigger mode                   */
  93 #define LVT_MASK       0x010000         /* Mask bit                             */
  94 #define LVT_TMM_PERIOD 0x020000         /* Periodic timer mode                  */
  95
  96 /* Timer divisors */
  97 #define TIMER_DIV_1   0x0B
  98 #define TIMER_DIV_2   0x00
  99 #define TIMER_DIV_4   0x01
 100 #define TIMER_DIV_8   0x02
 101 #define TIMER_DIV_16  0x03
 102 #define TIMER_DIV_32  0x08
 103 #define TIMER_DIV_64  0x09
 104 #define TIMER_DIV_128 0x0A
 105
 106 /* Register access macro to make the code more readable */
 107 #define APIC_REG(base, reg) *((volatile ULONG *)(base + reg))