rom/usb/pciusb/pciusb.h

   1 #ifndef PCIUSB_H
   2 #define PCIUSB_H
   3
   4 /*
   5  *----------------------------------------------------------------------------
   6  *                         Includes for pciusb.device
   7  *----------------------------------------------------------------------------
   8  *                   By Chris Hodges <chrisly@platon42.de>
   9  */
  10
  11 #include LC_LIBDEFS_FILE
  12
  13 #include <aros/libcall.h>
  14 #include <aros/asmcall.h>
  15 #include <aros/symbolsets.h>
  16
  17 #include <exec/types.h>
  18 #include <exec/lists.h>
  19 #include <exec/memory.h>
  20 #include <exec/libraries.h>
  21 #include <exec/interrupts.h>
  22 #include <exec/semaphores.h>
  23 #include <exec/execbase.h>
  24 #include <exec/devices.h>
  25 #include <exec/io.h>
  26 #include <exec/ports.h>
  27 #include <exec/errors.h>
  28 #include <exec/resident.h>
  29 #include <exec/initializers.h>
  30 #include <dos/dos.h>
  31
  32 #include <devices/timer.h>
  33 #include <utility/utility.h>
  34
  35 #include <devices/usbhardware.h>
  36 #include <devices/newstyle.h>
  37
  38 #include <oop/oop.h>
  39
  40 #include "debug.h"
  41
  42 #ifdef AROS_USB30_CODE
  43 #undef AROS_USB30_CODE
  44 #endif
  45
  46 /* Reply the iorequest with success */
  47 #define RC_OK         0
  48
  49 /* Magic cookie, don't set error fields & don't reply the ioreq */
  50 #define RC_DONTREPLY  -1
  51
  52 #define MAX_ROOT_PORTS   16
  53 #define MAX_USB3_PORTS   255
  54
  55 #define PCI_CLASS_SERIAL_USB 0x0c03
  56
  57 /* The unit node - private */
  58 struct PCIUnit
  59 {
  60     struct Unit           hu_Unit;
  61     LONG                  hu_UnitNo;
  62
  63     struct PCIDevice     *hu_Device;         /* Uplink */
  64
  65     struct MsgPort       *hu_MsgPort;
  66     struct timerequest   *hu_TimerReq;       /* Timer I/O Request */
  67
  68     struct timerequest    hu_LateIOReq;      /* Timer I/O Request */
  69     struct MsgPort        hu_LateMsgPort;
  70
  71     struct timerequest    hu_NakTimeoutReq;
  72     struct MsgPort        hu_NakTimeoutMsgPort;
  73     struct Interrupt      hu_NakTimeoutInt;
  74
  75     BOOL                  hu_UnitAllocated;  /* Unit opened */
  76
  77     ULONG                 hu_DevID;          /* Device ID (BusID+DevNo) */
  78     struct List           hu_Controllers;    /* List of controllers */
  79     UWORD                 hu_RootHub11Ports;
  80     UWORD                 hu_RootHub20Ports;
  81 #ifdef AROS_USB30_CODE
  82     UWORD                 hu_RootHub30Ports;
  83 #endif
  84     UWORD                 hu_RootHubPorts;
  85     UWORD                 hu_RootHubAddr;    /* Root Hub Address */
  86     UWORD                 hu_RootPortChanges; /* Merged root hub changes */
  87     ULONG                 hu_FrameCounter;   /* Common frame counter */
  88     struct List           hu_RHIOQueue;      /* Root Hub Pending IO Requests */
  89
  90     struct PCIController *hu_PortMap11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 controller */
  91     struct PCIController *hu_PortMap20[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 2.0 controller */
  92 #ifdef AROS_USB30_CODE
  93     struct PCIController *hu_PortMap30[MAX_USB3_PORTS]; /* Maps from Global Port to USB 3.0 controller */
  94 #endif
  95     UBYTE                 hu_PortNum11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 companion controller port */
  96     UBYTE                 hu_EhciOwned[MAX_ROOT_PORTS]; /* TRUE, if currently owned by EHCI */
  97     UBYTE                 hu_ProductName[80]; /* for Query device */
  98     struct PCIController *hu_DevControllers[128]; /* maps from Device address to controller */
  99     struct IOUsbHWReq    *hu_DevBusyReq[128*16*2]; /* pointer to io assigned to the Endpoint */
 100     ULONG                 hu_NakTimeoutFrame[128*16*2]; /* Nak Timeout framenumber */
 101     UBYTE                 hu_DevDataToggle[128*16*2]; /* Data toggle bit for endpoints */
 102 };
 103
 104 #define HCITYPE_UHCI     0x00
 105 #define HCITYPE_OHCI     0x10
 106 #define HCITYPE_EHCI     0x20
 107 #ifdef AROS_USB30_CODE
 108 #define HCITYPE_XHCI     0x30
 109 #endif
 110
 111 struct PCIController
 112 {
 113     struct Node           hc_Node;
 114     struct PCIDevice     *hc_Device;        /* Uplink */
 115     struct PCIUnit       *hc_Unit;          /* Uplink */
 116
 117     OOP_Object           *hc_PCIDeviceObject;
 118     OOP_Object           *hc_PCIDriverObject;
 119     ULONG                 hc_DevID;
 120     UWORD                 hc_FunctionNum;
 121     UWORD                 hc_HCIType;
 122     UWORD                 hc_NumPorts;
 123     UWORD                 hc_Flags;         /* See below */
 124
 125     volatile APTR         hc_RegBase;
 126
 127     #ifdef AROS_USB30_CODE
 128     volatile APTR         xhc_capregbase;
 129     volatile APTR         xhc_opregbase;
 130     volatile APTR         xhc_doorbellbase;
 131     volatile APTR         xhc_runtimebase;
 132
 133     ULONG                 xhc_pagesize;
 134
 135     ULONG                 xhc_maxslots;
 136
 137     UQUAD                *xhc_dcbaa;
 138     ULONG                 xhc_scratchpads;
 139     UQUAD                *xhc_scratchpadarray;
 140
 141     BOOL                  xhc_contextsize64;
 142
 143     UWORD                 xhc_NumPorts;
 144     UWORD                 xhc_NumPorts20;
 145     UWORD                 xhc_NumPorts30;
 146     #endif
 147
 148     APTR                  hc_PCIMem;
 149     ULONG                 hc_PCIMemSize;
 150     IPTR                  hc_PCIVirtualAdjust;
 151     IPTR                  hc_PCIIntLine;
 152     struct Interrupt      hc_PCIIntHandler;
 153     ULONG                 hc_PCIIntEnMask;
 154
 155     ULONG                *hc_UhciFrameList;
 156     struct UhciQH        *hc_UhciQHPool;
 157     struct UhciTD        *hc_UhciTDPool;
 158
 159     struct UhciQH        *hc_UhciCtrlQH;
 160     struct UhciQH        *hc_UhciBulkQH;
 161     struct UhciQH        *hc_UhciIntQH[9];
 162     struct UhciTD        *hc_UhciIsoTD;
 163     struct UhciQH        *hc_UhciTermQH;
 164
 165     ULONG                 hc_EhciUsbCmd;
 166     ULONG                *hc_EhciFrameList;
 167     struct EhciQH        *hc_EhciQHPool;
 168     struct EhciTD        *hc_EhciTDPool;
 169
 170     struct EhciQH        *hc_EhciAsyncQH;
 171     struct EhciQH        *hc_EhciIntQH[11];
 172     struct EhciQH        *hc_EhciTermQH;
 173     volatile BOOL         hc_AsyncAdvanced;
 174     struct EhciQH        *hc_EhciAsyncFreeQH;
 175     struct EhciTD        *hc_ShortPktEndTD;
 176
 177     struct OhciED        *hc_OhciCtrlHeadED;
 178     struct OhciED        *hc_OhciCtrlTailED;
 179     struct OhciED        *hc_OhciBulkHeadED;
 180     struct OhciED        *hc_OhciBulkTailED;
 181     struct OhciED        *hc_OhciIntED[5];
 182     struct OhciED        *hc_OhciTermED;
 183     struct OhciTD        *hc_OhciTermTD;
 184     struct OhciHCCA      *hc_OhciHCCA;
 185     struct OhciED        *hc_OhciEDPool;
 186     struct OhciTD        *hc_OhciTDPool;
 187     struct OhciED        *hc_OhciAsyncFreeED;
 188     ULONG                 hc_OhciDoneQueue;
 189     struct List           hc_OhciRetireQueue;
 190
 191     ULONG                 hc_FrameCounter;
 192     struct List           hc_TDQueue;
 193     struct List           hc_AbortQueue;
 194     struct List           hc_PeriodicTDQueue;
 195     struct List           hc_CtrlXFerQueue;
 196     struct List           hc_IntXFerQueue;
 197     struct List           hc_IsoXFerQueue;
 198     struct List           hc_BulkXFerQueue;
 199
 200     struct Interrupt      hc_CompleteInt;
 201     struct Interrupt      hc_ResetInt;
 202
 203     UBYTE                 hc_PortNum20[MAX_ROOT_PORTS];     /* Global Port number the local controller port corresponds with */
 204
 205     UWORD                 hc_PortChangeMap[MAX_ROOT_PORTS]; /* Port Change Map */
 206
 207     BOOL                  hc_complexrouting;
 208     ULONG                 hc_portroute;
 209
 210 };
 211
 212 /* hc_Flags */
 213 #define HCF_ALLOCATED   0x0001  /* PCI board allocated           */
 214 #define HCF_ONLINE      0x0002  /* Online                        */
 215 #define HCF_STOP_BULK   0x0004  /* Bulk transfers stopped        */
 216 #define HCF_STOP_CTRL   0x0008  /* Control transfers stopped     */
 217 #define HCF_ABORT       0x0010  /* Aborted requests available    */
 218
 219 /* The device node - private
 220 */
 221 struct PCIDevice
 222 {
 223     struct Library      hd_Library;       /* standard */
 224     UWORD               hd_Flags;         /* various flags */
 225
 226     struct UtilityBase *hd_UtilityBase;   /* for tags etc */
 227
 228     struct List         hd_TempHCIList;
 229     OOP_Object         *hd_PCIHidd;
 230     OOP_AttrBase        hd_HiddAB;
 231     OOP_AttrBase        hd_HiddPCIDeviceAB;
 232     OOP_MethodID        hd_HiddPCIDeviceMB;
 233
 234     BOOL                hd_ScanDone;      /* PCI scan done? */
 235     APTR                hd_MemPool;       /* Memory Pool */
 236
 237         struct List         hd_Units;         /* List of units */
 238 };
 239
 240 /* hd_Flags */
 241 #define HDF_FORCEPOWER  0x01
 242
 243 #endif /* PCIUSB_H */