rom/hidds/pci/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 /*
   5     Copyright © 2004-2014, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/libraries.h>
  11 #include <exec/execbase.h>
  12 #include <exec/nodes.h>
  13 #include <exec/lists.h>
  14 #include <exec/semaphores.h>
  15 #include <dos/bptr.h>
  16
  17 #include <aros/libcall.h>
  18 #include <aros/asmcall.h>
  19
  20 #include <oop/oop.h>
  21
  22 #include <exec/execbase.h>
  23
  24 #include LC_LIBDEFS_FILE
  25
  26 /* Private data and structures unavailable outside the pci base classes */
  27
  28 struct DrvInstData {
  29     BOOL DirectBus;
  30     IPTR IOBase;
  31 };
  32
  33 typedef struct DeviceData {
  34     struct MinNode      node;           /* Accessed directly by PCI subsystem class */
  35     OOP_Object          *driver;
  36     UBYTE               bus,dev,sub;
  37     UBYTE               isBridge;
  38     UBYTE               subbus;
  39     UWORD               VendorID;
  40     UWORD               ProductID;
  41     UBYTE               RevisionID;
  42     UBYTE               Interface;
  43     UBYTE               SubClass;
  44     UBYTE               Class;
  45     UWORD               SubsysVID;
  46     UWORD               SubsystemID;
  47     UBYTE               INTLine;
  48     UBYTE               IRQLine;
  49     UBYTE               HeaderType;
  50     struct {
  51         IPTR            addr;
  52         IPTR            size;
  53     } BaseReg[6];
  54     ULONG               RomBase;
  55     ULONG               RomSize;
  56
  57     STRPTR              strClass;
  58     STRPTR              strSubClass;
  59     STRPTR              strInterface;
  60
  61     struct SignalSemaphore ownerLock;
  62
  63     /* If Extended Configuration exists, the HW driver fills this with a
  64        non-NULL value */
  65     IPTR                extendedconfig;
  66
  67 } tDeviceData;
  68
  69 struct pci_staticdata {
  70     struct SignalSemaphore dev_lock;
  71     struct MinList      devices;        /* List of devices */
  72
  73     APTR                kernelBase;
  74     struct Library      *utilityBase;
  75     struct Library      *oopBase;
  76
  77     OOP_AttrBase        hwAttrBase;
  78     OOP_AttrBase        hiddPCIAB;
  79     OOP_AttrBase        hiddPCIDriverAB;
  80     OOP_AttrBase        hiddPCIBusAB;
  81     OOP_AttrBase        hiddPCIDeviceAB;
  82     OOP_MethodID        hiddPCIDriverMB;
  83     OOP_MethodID        hwMethodBase;
  84
  85     OOP_Class           *pciClass;
  86     OOP_Class           *pciDeviceClass;
  87     OOP_Class           *pciDriverClass;
  88     OOP_Object          *pciObject;
  89
  90     BPTR                segList;
  91 };
  92
  93 struct pcibase {
  94     struct Library              LibNode;
  95     struct pci_staticdata       psd;
  96 };
  97
  98 OOP_Class *init_pcideviceclass(struct pci_staticdata *);
  99 void free_pcideviceclass(struct pci_staticdata *, OOP_Class *cl);
 100
 101 #define BASE(lib) ((struct pcibase*)(lib))
 102
 103 #define PSD(cl) (&BASE(cl->UserData)->psd)
 104
 105 /*
 106     There are no static AttrBases in this class. Therefore it might be placed
 107     directly in ROM without any harm
 108 */
 109 #undef HiddPCIAttrBase
 110 #undef HiddPCIDeviceAttrBase
 111 #undef HiddPCIDriverAttrBase
 112 #undef HWAttrBase
 113 #undef HiddPCIDriverBase
 114 #undef HWBase
 115
 116 #define HiddPCIAttrBase       (PSD(cl)->hiddPCIAB)
 117 #define HiddPCIDeviceAttrBase (PSD(cl)->hiddPCIDeviceAB)
 118 #define HiddPCIDriverAttrBase (PSD(cl)->hiddPCIDriverAB)
 119 #define HWAttrBase            (PSD(cl)->hwAttrBase)
 120 #define HiddPCIDriverBase     (PSD(cl)->hiddPCIDriverMB)
 121 #define HWBase                (PSD(cl)->hwMethodBase)
 122
 123 #define KernelBase (PSD(cl)->kernelBase)
 124 #define UtilityBase PSD(cl)->utilityBase
 125 #define OOPBase     PSD(cl)->oopBase
 126
 127 /* PCI Configspace offsets */
 128 #define PCICS_VENDOR        0x00
 129 #define PCICS_PRODUCT       0x02
 130 #define PCICS_COMMAND       0x04
 131 #define PCICS_STATUS        0x06
 132 #define PCICS_REVISION      0x08
 133 #define PCICS_PROGIF        0x09
 134 #define PCICS_SUBCLASS      0x0a
 135 #define PCICS_CLASS         0x0b
 136 #define PCICS_CACHELS       0x0c
 137 #define PCICS_LATENCY       0x0d
 138 #define PCICS_HEADERTYPE    0x0e
 139 #define PCICS_BIST          0x0f
 140 #define PCICS_BAR0          0x10
 141 #define PCICS_BAR1          0x14
 142 #define PCICS_BAR2          0x18
 143 #define PCICS_BAR3          0x1c
 144 #define PCICS_BAR4          0x20
 145 #define PCICS_BAR5          0x24
 146 #define PCICS_CARDBUS_CIS   0x28
 147 #define PCICS_SUBVENDOR     0x2c
 148 #define PCICS_SUBSYSTEM     0x2e
 149 #define PCICS_EXPROM_BASE   0x30
 150 #define PCICS_CAP_PTR       0x34
 151 #define PCICS_INT_LINE      0x3c
 152 #define PCICS_INT_PIN       0x3d
 153 #define PCICS_MIN_GNT       0x3e
 154 #define PCICS_MAX_LAT       0x3f
 155
 156 /* PCI Headertypes */
 157 #define PCIHT_MASK          0x7f
 158 #define PCIHT_MULTIFUNC     0x80
 159
 160 #define PCIHT_NORMAL        0x00
 161 #define PCIHT_BRIDGE        0x01
 162 #define PCIHT_CARDBUS       0x02
 163
 164 /* PCI Command register bits */
 165 #define PCICMB_IODECODE     0
 166 #define PCICMB_MEMDECODE    1
 167 #define PCICMB_BUSMASTER    2
 168 #define PCICMB_SPECIAL      3
 169 #define PCICMB_INVALIDATE   4
 170 #define PCICMB_VGASNOOP     5
 171 #define PCICMB_PARITY       6
 172 #define PCICMB_STEPPING     7
 173 #define PCICMB_SERR         8
 174 #define PCICMB_FASTB2B      9
 175
 176 #define PCICMF_IODECODE     (1 << PCICMB_IODECODE)
 177 #define PCICMF_MEMDECODE    (1 << PCICMB_MEMDECODE)
 178 #define PCICMF_BUSMASTER    (1 << PCICMB_BUSMASTER)
 179 #define PCICMF_SPECIAL      (1 << PCICMB_SPECIAL)
 180 #define PCICMF_INVALIDATE   (1 << PCICMB_INVALIDATE)
 181 #define PCICMF_VGASNOOP     (1 << PCICMB_VGASNOOP)
 182 #define PCICMF_PARITY       (1 << PCICMB_PARITY)
 183 #define PCICMF_STEPPING     (1 << PCICMB_STEPPING)
 184 #define PCICMF_SERR         (1 << PCICMB_SERR)
 185 #define PCICMF_FASTB2B      (1 << PCICMB_FASTB2B)
 186
 187 /* PCI Status register bits */
 188 #define PCISTB_INTERRUPT_STATUS 3       /* might be AHCI specific */
 189 #define PCISTB_CAPABILITES      4
 190 #define PCISTB_66MHZ            5
 191 #define PCISTB_FASTB2B          7
 192 #define PCISTB_PARITY           8
 193 #define PCISTB_SIG_TGT_ABORT    11
 194 #define PCISTB_REC_TGT_ABORT    12
 195 #define PCISTB_REC_MAS_ABORT    13
 196 #define PCISTB_SIG_SYSERR       14
 197 #define PCISTB_PARITYERR        15
 198
 199 #define PCISTF_INTERRUPT_STATUS (1 << PCISTB_INTERRUPT_STATUS)
 200 #define PCISTF_CAPABILITIES     (1 << PCISTB_CAPABILITES)
 201 #define PCISTF_66MHZ            (1 << PCISTB_66MHZ)
 202 #define PCISTF_FASTB2B          (1 << PCISTB_FASTB2B)
 203 #define PCISTF_PARITY           (1 << PCISTB_PARITY)
 204 #define PCISTF_SIG_TGT_ABORT    (1 << PCISTB_SIG_TGT_ABORT)
 205 #define PCISTF_REC_TGT_ABORT    (1 << PCISTB_REC_TGT_ABORT)
 206 #define PCISTF_REC_MAS_ABORT    (1 << PCISTB_REC_MAS_ABORT)
 207 #define PCISTF_SIG_SYSERR       (1 << PCISTB_SIG_SYSERR)
 208 #define PCISTF_PARITYERR        (1 << PCISTB_PARITYERR)
 209
 210 #define PCIST_DEVSEL_MASK   0x600
 211 #define PCIST_DEVSEL_FAST   0x000
 212 #define PCIST_DEVSEL_MEDIUM 0x200
 213 #define PCIST_DEVSEL_SLOW   0x400
 214
 215 /* PCI BIST register */
 216 #define PCIBSB_START            6
 217 #define PCIBSB_CAPABLE          7
 218
 219 #define PCIBSF_START            (1 << PCIBSB_START)
 220 #define PCIBSF_CAPABLE          (1 << PCIBSB_CAPABLE)
 221
 222 #define PCIBS_CODEMASK          0x0f
 223
 224 /* PCI BaseAddressRegister defines */
 225 #define PCIBAR_MASK_TYPE        0x01
 226 #define PCIBAR_TYPE_MMAP        0x00
 227 #define PCIBAR_TYPE_IO          0x01
 228 #define PCIBAR_MASK_MEM         0xfffffff0
 229 #define PCIBAR_MASK_IO          0xfffffffc
 230
 231 #define PCIBAR_MEMTYPE_MASK     0x06
 232 #define PCIBAR_MEMTYPE_32BIT    0x00
 233 #define PCIBAR_MEMTYPE_64BIT    0x04
 234
 235 #define PCIBARB_PREFETCHABLE    3
 236 #define PCIBARF_PREFETCHABLE    (1 << PCIBARB_PREFETCHABLE)
 237
 238 /*
 239  * PCI-to-PCI bridge header defines
 240  * First 16 bytes are the same as normal PCI dev
 241  * Use either PCICS_ or PCIBR_ prefix
 242  */
 243 #define PCIBR_VENDOR        PCICS_VENDOR
 244 #define PCIBR_PRODUCT       PCICS_PRODUCT
 245 #define PCIBR_COMMAND       PCICS_COMMAND
 246 #define PCIBR_STATUS        PCICS_STATUS
 247 #define PCIBR_REVISION      PCICS_REVISION
 248 #define PCIBR_PROGIF        PCICS_PROGIF
 249 #define PCIBR_SUBCLASS      PCICS_SUBCLASS
 250 #define PCIBR_CLASS         PCICS_CLASS
 251 #define PCIBR_CACHELS       PCICS_CACHELS
 252 #define PCIBR_LATENCY       PCICS_LATENCY
 253 #define PCIBR_HEADERTYPE    PCICS_HEADERTYPE
 254 #define PCIBR_BIST          PCICS_BIST
 255 #define PCIBR_BAR0          0x10
 256 #define PCIBR_BAR1          0x14
 257 #define PCIBR_PRIBUS        0x18
 258 #define PCIBR_SECBUS        0x19
 259 #define PCIBR_SUBBUS        0x1a
 260 #define PCIBR_SECLATENCY    0x1b
 261 #define PCIBR_IOBASE        0x1c
 262 #define PCIBR_IOLIMIT       0x1d
 263 #define PCIBR_SECSTATUS     0x1e
 264 #define PCIBR_MEMBASE       0x20
 265 #define PCIBR_MEMLIMIT      0x22
 266 #define PCIBR_PREFETCHBASE  0x24
 267 #define PCIBR_PREFETCHLIMIT 0x26
 268 #define PCIBR_PREBASEUPPER  0x28
 269 #define PCIBR_PRELIMITUPPER 0x2c
 270 #define PCIBR_IOBASEUPPER   0x30
 271 #define PCIBR_IOLIMITUPPER  0x32
 272 #define PCIBR_CAPPTR        0x34
 273 #define PCIBR_EXPROMBASE    0x38
 274 #define PCIBR_INT_LINE      0x3c
 275 #define PCIBR_INT_PIN       0x3d
 276 #define PCIBR_CONTROL       0x3e
 277
 278 #define PCICTRLB_ISAENABLE      2
 279 #define PCICTRLB_VGAENABLE      3
 280
 281 #define PCICTRLF_ISAENABLE          (1 << PCICTRLB_ISAENABLE)
 282 #define PCICTRLF_VGAENABLE          (1 << PCICTRLB_VGAENABLE)
 283
 284 /* PCI capabilities */
 285 #define PCICAP_POWER_MANAGEMENT     0x01
 286 #define PCICAP_AGP                  0x02
 287 #define PCICAP_VITAL_PRODUCT_DATA   0x03
 288 #define PCICAP_SLOT_ID              0x04
 289 #define PCICAP_MSI                  0x05
 290 #define PCICAP_CPCI_HOT_SWAP        0x06
 291 #define PCICAP_PCIX                 0x07
 292 #define PCICAP_HYPER_TRANSPORT      0x08
 293 #define PCICAP_VENDOR_SPECIFIC      0x09
 294 #define PCICAP_DEBUG_PORT           0x0a
 295 #define PCICAP_CPCI_CR              0x0b
 296 #define PCICAP_HOT_PLUG_CONTROLLER  0x0c
 297 #define PCICAP_SSVPID               0x0d
 298 #define PCICAP_AGP3                 0x0e
 299 #define PCICAP_PCIE                 0x10
 300 #define PCICAP_MSIX                 0x11
 301 #define PCICAP_ADVANCED_FEATURES    0x13
 302
 303 #endif /* _PCI_H */
 304