arch/all-darwin/kernel/cpu_arm.h

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <exec/types.h>
   7 #include <aros/arm/cpucontext.h>
   8
   9 #ifdef __AROS_EXEC_LIBRARY__
  10
  11 /* regs_t is a black box here */
  12 struct ucontext;
  13 typedef struct ucontext *regs_t;
  14
  15 #else
  16
  17 #include <sys/ucontext.h>
  18
  19 #define SIGCORE_NEED_SA_SIGINFO
  20
  21 typedef ucontext_t regs_t;
  22
  23 #define SIGHANDLER      bsd_sighandler
  24 typedef void (*SIGHANDLER_T)(int);
  25
  26 #define SC_DISABLE(sc)   sc->uc_sigmask = KernelBase->kb_PlatformData->sig_int_mask
  27 #define SC_ENABLE(sc)                           \
  28 do {                                            \
  29     KernelIFace.SigEmptySet(&(sc)->uc_sigmask); \
  30     AROS_HOST_BARRIER                           \
  31 } while(0)
  32
  33 /* work around silly renaming of struct members in OS X 10.5 */
  34 #if __DARWIN_UNIX03
  35
  36 #define R0(context)     ((context)->uc_mcontext->__ss.__r[0])
  37 #define R1(context)     ((context)->uc_mcontext->__ss.__r[1])
  38 #define R2(context)     ((context)->uc_mcontext->__ss.__r[2])
  39 #define R3(context)     ((context)->uc_mcontext->__ss.__r[3])
  40 #define R4(context)     ((context)->uc_mcontext->__ss.__r[4])
  41 #define R5(context)     ((context)->uc_mcontext->__ss.__r[5])
  42 #define R6(context)     ((context)->uc_mcontext->__ss.__r[6])
  43 #define R7(context)     ((context)->uc_mcontext->__ss.__r[7])
  44 #define R8(context)     ((context)->uc_mcontext->__ss.__r[8])
  45 #define R9(context)     ((context)->uc_mcontext->__ss.__r[9])
  46 #define R10(context)    ((context)->uc_mcontext->__ss.__r[10])
  47 #define R11(context)    ((context)->uc_mcontext->__ss.__r[11])
  48 #define R12(context)    ((context)->uc_mcontext->__ss.__r[12])
  49 #define SP(context)     ((context)->uc_mcontext->__ss.__sp)
  50 #define LR(context)     ((context)->uc_mcontext->__ss.__lr)
  51 #define PC(context)     ((context)->uc_mcontext->__ss.__pc)
  52 #define CPSR(context)   ((context)->uc_mcontext->__ss.__cpsr)
  53
  54 #define GPSTATE(context) ((context)->uc_mcontext->__ss)
  55 #define FPSTATE(context) ((context)->uc_mcontext->__fs)
  56
  57 #else
  58
  59 #define R0(context)     ((context)->uc_mcontext->ss.r[0])
  60 #define R1(context)     ((context)->uc_mcontext->ss.r[1])
  61 #define R2(context)     ((context)->uc_mcontext->ss.r[2])
  62 #define R3(context)     ((context)->uc_mcontext->ss.r[3])
  63 #define R4(context)     ((context)->uc_mcontext->ss.r[4])
  64 #define R5(context)     ((context)->uc_mcontext->ss.r[5])
  65 #define R6(context)     ((context)->uc_mcontext->ss.r[6])
  66 #define R7(context)     ((context)->uc_mcontext->ss.r[7])
  67 #define R8(context)     ((context)->uc_mcontext->ss.r[8])
  68 #define R9(context)     ((context)->uc_mcontext->ss.r[9])
  69 #define R10(context)    ((context)->uc_mcontext->ss.r[10])
  70 #define R11(context)    ((context)->uc_mcontext->ss.r[11])
  71 #define R12(context)    ((context)->uc_mcontext->ss.r[12])
  72 #define SP(context)     ((context)->uc_mcontext->ss.sp)
  73 #define LR(context)     ((context)->uc_mcontext->ss.lr)
  74 #define PC(context)     ((context)->uc_mcontext->ss.pc)
  75 #define CPSR(context)   ((context)->uc_mcontext->ss.cpsr)
  76
  77 #define GPSTATE(context) ((context)->uc_mcontext->ss)
  78 #define FPSTATE(context) ((context)->uc_mcontext->fs)
  79
  80 #endif
  81
  82 #define GLOBAL_SIGNAL_INIT(sighandler) \
  83         static void sighandler ## _gate (int sig, int code, ucontext_t *sc) \
  84         {                                                    \
  85             sighandler(sig, sc);                             \
  86         }
  87
  88 /*
  89  * SAVEREGS and RESTOREREGS rely on the fact that layout of
  90  * struct ExceptionContext is actually the same as layout of
  91  * Darwin's context.
  92  */
  93 #define SAVEREGS(cc, sc)                                                                \
  94     CopyMemQuick(&GPSTATE(sc), (cc)->regs.r, sizeof(_STRUCT_ARM_THREAD_STATE));         \
  95     if ((cc)->regs.fpuContext)                                                          \
  96     {                                                                                   \
  97         (cc)->regs.Flags |= ECF_FPU;                                                    \
  98         CopyMemQuick(&FPSTATE(sc), (cc)->regs.fpuContext, sizeof(struct VFPContext));   \
  99     }
 100
 101 #define RESTOREREGS(cc, sc)                                                     \
 102     CopyMemQuick((cc)->regs.r, &GPSTATE(sc), sizeof(_STRUCT_ARM_THREAD_STATE)); \
 103     if ((cc)->regs.Flags & ECF_FPU)                                             \
 104         CopyMemQuick((cc)->regs.fpuContext, &FPSTATE(sc), sizeof(struct VFPContext));
 105
 106 /* Print signal context. Used in crash handler */
 107 #define PRINT_SC(sc) \
 108     bug ("    R0=%08X  R1=%08X  R2 =%08X  R3 =%08X\n" \
 109          "    R4=%08X  R5=%08X  R6 =%08X  R7 =%08X\n" \
 110          "    R8=%08X  R9=%08X  R10=%08X  R11=%08X\n" \
 111          "    IP=%08X  SP=%08X  LR =%08X  PC =%08X\n" \
 112          "    CPSR=%08X\n"                            \
 113             , R0(sc), R1(sc), R2(sc), R3(sc)    \
 114             , R4(sc), R5(sc), R6(sc), R7(sc)    \
 115             , R8(sc), R9(sc), R10(sc), R11(sc)  \
 116             , R12(sc), SP(sc), LR(sc), PC(sc)   \
 117             , CPSR(sc)                          \
 118         )
 119
 120 #endif /* __AROS_EXEC_LIBRARY__ */
 121
 122 /* We emulate 6 exceptions of ARM CPU (all but softint) */
 123 #define EXCEPTIONS_COUNT 6
 124
 125 struct AROSCPUContext
 126 {
 127     struct ExceptionContext regs;
 128     int errno_backup;
 129 };
 130
 131 /* Darwin supports only VFP */
 132 #define ARM_FPU_TYPE FPU_VFP
 133 #define ARM_FPU_SIZE sizeof(struct VFPContext)