arch/all-pc/kernel/apic_ia32.c

   1 /*
   2     Copyright � 1995-2017, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: Intel IA-32 APIC driver.
   6 */
   7
   8 #include <aros/macros.h>
   9 #include <asm/cpu.h>
  10 #include <asm/io.h>
  11 #include <exec/types.h>
  12
  13 #define __KERNEL_NOLIBBASE__
  14 #include <proto/kernel.h>
  15
  16 #include <proto/exec.h>
  17
  18 #include <inttypes.h>
  19
  20 #include "kernel_base.h"
  21 #include "kernel_intern.h"
  22 #include "kernel_objects.h"
  23 #include "kernel_debug.h"
  24 #include "kernel_syscall.h"
  25 #include "kernel_timer.h"
  26
  27 #include "kernel_interrupts.h"
  28
  29 #include "apic_ia32.h"
  30
  31 #define D(x)
  32 #define DINT(x)
  33 #define DWAKE(x)        /* Badly interferes with AP startup */
  34 #define DID(x)          /* Badly interferes with everything */
  35 /* #define DEBUG_WAIT */
  36
  37 /*
  38  * On i386 platform we need to support various quirks of old APICs.
  39  * x86-64 is free of that crap.
  40  */
  41 #ifdef __i386__
  42 #define CONFIG_LEGACY
  43 #endif
  44
  45 extern void core_APICErrorHandle(struct ExceptionContext *, void *, void *);
  46 AROS_INTP(APICHeartbeatServer);
  47
  48 /* APIC Interrupt Controller Functions ... ***************************/
  49
  50 struct APICInt_Private
  51 {
  52
  53 };
  54
  55 icid_t APICInt_Register(struct KernelBase *KernelBase)
  56 {
  57     DINT(bug("[Kernel:APIC-IA32] %s()\n", __func__));
  58
  59     return (icid_t)APICInt_IntrController.ic_Node.ln_Type;
  60 }
  61
  62 BOOL APICInt_Init(struct KernelBase *KernelBase, icid_t instanceCount)
  63 {
  64     struct PlatformData *kernPlatD = (struct PlatformData *)KernelBase->kb_PlatformData;
  65     struct APICData *apicPrivate = kernPlatD->kb_APIC;
  66     APTR ssp;
  67     int irq;
  68
  69     DINT(bug("[Kernel:APIC-IA32] %s(%d)\n", __func__, instanceCount));
  70
  71     /* its not fatal to fail on these irqs... */
  72     if ((ssp = SuperState()) != NULL)
  73     {
  74         /* Setup the APIC IRQs for CPU #0*/
  75         for (irq = (APIC_IRQ_BASE - X86_CPU_EXCEPT_COUNT); irq < ((APIC_IRQ_BASE - X86_CPU_EXCEPT_COUNT) + APIC_IRQ_COUNT); irq++)
  76         {
  77             if (!krnInitInterrupt(KernelBase, irq, APICInt_IntrController.ic_Node.ln_Type, 0))
  78             {
  79                 D(bug("[Kernel:APIC-IA32] %s: failed to obtain IRQ %d\n", __func__, irq);)
  80             }
  81             else
  82             {
  83                 /* dont enable the vector yet...*/
  84                 if (!core_SetIDTGate((apicidt_t *)apicPrivate->cores[0].cpu_IDT, HW_IRQ_BASE + irq, (uintptr_t)IntrDefaultGates[HW_IRQ_BASE + irq], FALSE))
  85                 {
  86                     bug("[Kernel:APIC-IA32] %s: failed to set IRQ %d's Vector gate\n", __func__, irq);
  87                 }
  88             }
  89         }
  90         UserState(ssp);
  91     }
  92
  93     return TRUE;
  94 }
  95
  96 BOOL APICInt_DisableIRQ(APTR icPrivate, icid_t icInstance, icid_t intNum)
  97 {
  98     struct PlatformData *kernPlatD = (struct PlatformData *)KernelBase->kb_PlatformData;
  99     struct APICData *apicPrivate = kernPlatD->kb_APIC;
 100     apicidt_t *IGATES;
 101     APTR ssp;
 102
 103     DINT(bug("[Kernel:APIC-IA32] %s(%03u #$%02X)\n", __func__, icInstance, intNum));
 104
 105     IGATES = (apicidt_t *)apicPrivate->cores[icInstance].cpu_IDT;
 106
 107     if ((ssp = SuperState()) != NULL)
 108     {
 109         IGATES[HW_IRQ_BASE + intNum].p = 0;
 110         UserState(ssp);
 111     }
 112
 113     return TRUE;
 114 }
 115
 116 BOOL APICInt_EnableIRQ(APTR icPrivate, icid_t icInstance, icid_t intNum)
 117 {
 118     struct PlatformData *kernPlatD = (struct PlatformData *)KernelBase->kb_PlatformData;
 119     struct APICData *apicPrivate = kernPlatD->kb_APIC;
 120     apicidt_t *IGATES;
 121     APTR ssp;
 122
 123     DINT(bug("[Kernel:APIC-IA32] %s(%03u #$%02X)\n", __func__, icInstance, intNum));
 124
 125     IGATES = (apicidt_t *)apicPrivate->cores[icInstance].cpu_IDT;
 126
 127     if ((ssp = SuperState()) != NULL)
 128     {
 129         IGATES[HW_IRQ_BASE + intNum].p = 1;
 130         UserState(ssp);
 131     }
 132
 133     return TRUE;
 134 }
 135
 136 BOOL APICInt_AckIntr(APTR icPrivate, icid_t icInstance, icid_t intNum)
 137 {
 138     IPTR apic_base;
 139
 140     DINT(bug("[Kernel:APIC-IA32] %s(%03u #$%02X)\n", __func__, icInstance, intNum));
 141
 142     /* Write zero to EOI of APIC */
 143     apic_base = core_APIC_GetBase();
 144
 145     APIC_REG(apic_base, APIC_EOI) = 0;
 146
 147     return TRUE;
 148 }
 149
 150 struct IntrController APICInt_IntrController =
 151 {
 152     {
 153         .ln_Name = "x86 Local APIC",
 154         .ln_Pri = -50
 155     },
 156     0,
 157     AROS_MAKE_ID('A','P','I','C'),
 158     0,
 159     NULL,
 160     APICInt_Register,
 161     APICInt_Init,
 162     APICInt_EnableIRQ,
 163     APICInt_DisableIRQ,
 164     APICInt_AckIntr
 165 };
 166
 167 /* APIC IPI Related Functions ... ***************************/
 168
 169 static ULONG DoIPI(IPTR __APICBase, ULONG target, ULONG cmd)
 170 {
 171     ULONG ipisend_timeout, status_ipisend;
 172
 173     D(
 174         apicid_t cpuNum = KrnGetCPUNumber();
 175         bug("[Kernel:APIC-IA32.%03u] %s: Command 0x%08X to target %03u\n", cpuNum, __func__, cmd, target);
 176     )
 177
 178     /*
 179      * Send the IPI.
 180      * First we write target APIC ID into high command register.
 181      * Writing to the low register triggers the IPI itself.
 182      */
 183     APIC_REG(__APICBase, APIC_ICRH) = target << 24;
 184     APIC_REG(__APICBase, APIC_ICRL) = cmd;
 185
 186     D(bug("[Kernel:APIC-IA32.%03u] %s: Waiting for IPI to complete ", cpuNum, __func__));
 187
 188     for (ipisend_timeout = 1000; ipisend_timeout > 0; ipisend_timeout--)
 189     {
 190         pit_udelay(100);
 191 #ifdef DEBUG_WAIT
 192         if ((ipisend_timeout % 100) == 0)
 193         {
 194             bug(".");
 195         }
 196 #endif
 197         status_ipisend = APIC_REG(__APICBase, APIC_ICRL) & ICR_DS;
 198         /* Delivery status resets to 0 when delivery is done */
 199         if (status_ipisend == 0)
 200             break;
 201     }
 202     D(bug("\n"));
 203     D(bug("[Kernel:APIC-IA32.%03u] %s: ... left wait loop (status = 0x%08X)\n", cpuNum, __func__, status_ipisend));
 204
 205     return status_ipisend;
 206 }
 207
 208 /**********************************************************
 209                         Driver functions
 210  **********************************************************/
 211
 212 void core_APIC_Init(struct APICData *apic, apicid_t cpuNum)
 213 {
 214     IPTR __APICBase = apic->lapicBase;
 215     ULONG apic_ver = APIC_REG(__APICBase, APIC_VERSION);
 216     ULONG maxlvt = APIC_LVT(apic_ver), calibrated = 0;
 217     LONG lapic_initial, lapic_final;
 218     WORD pit_final;
 219     icintrid_t coreICInstID;
 220
 221 #ifdef CONFIG_LEGACY
 222     /* 82489DX doesnt report no. of LVT entries. */
 223     if (!APIC_INTEGRATED(apic_ver))
 224         maxlvt = 2;
 225 #endif
 226
 227     if ((coreICInstID = krnAddInterruptController(KernelBase, &APICInt_IntrController)) != (icintrid_t)-1)
 228     {
 229         APTR ssp = NULL;
 230         int i;
 231
 232         D(bug("[Kernel:APIC-IA32.%03u] %s: APIC IC ID #%d:%d\n", cpuNum, __func__, ICINTR_ICID(coreICInstID), ICINTR_INST(coreICInstID)));
 233
 234         /*
 235          * NB: - BSP calls us in user mode, but AP's call us from supervisor
 236          */
 237         if ((KrnIsSuper()) || ((ssp = SuperState()) != NULL))
 238         {
 239             /* Obtain/set the critical IRQs and Vectors */
 240             for (i = 0; i < X86_CPU_EXCEPT_COUNT; i++)
 241             {
 242                 if ((HW_IRQ_BASE < i) && (cpuNum == 0))
 243                 {
 244                     if (!krnInitInterrupt(KernelBase, (i - HW_IRQ_BASE), APICInt_IntrController.ic_Node.ln_Type, 0))
 245                     {
 246                         krnPanic(NULL, "Failed to obtain APIC Exception IRQ\n"
 247                                        "IRQ #$%02X\n", (i - HW_IRQ_BASE));
 248                     }
 249                     if (!core_SetIRQGate(apic->cores[cpuNum].cpu_IDT, (i - HW_IRQ_BASE), (uintptr_t)IntrDefaultGates[i]))
 250                     {
 251                         krnPanic(NULL, "Failed to set APIC Exception IRQ Vector\n"
 252                                        "IRQ #$%02X, Vector #$%02X\n", (i - HW_IRQ_BASE), i);
 253                     }
 254                 }
 255                 else if (!core_SetIDTGate((apicidt_t *)apic->cores[cpuNum].cpu_IDT, i, (uintptr_t)IntrDefaultGates[i], TRUE))
 256                 {
 257                     krnPanic(NULL, "Failed to set APIC Exception Vector\n"
 258                                    "Vector #$%02X\n", i);
 259                 }
 260             }
 261             D(bug("[Kernel:APIC-IA32.%03u] %s: APIC Exception Vectors configured\n", cpuNum, __func__));
 262
 263             if ((APIC_IRQ_ERROR < HW_IRQ_COUNT) && (cpuNum == 0))
 264             {
 265                 if (!krnInitInterrupt(KernelBase, (APIC_IRQ_ERROR - HW_IRQ_BASE), APICInt_IntrController.ic_Node.ln_Type, 0))
 266                 {
 267                     krnPanic(NULL, "Failed to obtain APIC Error IRQ\n"
 268                                    "IRQ #$%02X\n", (APIC_IRQ_ERROR - HW_IRQ_BASE));
 269                 }
 270                 if (!core_SetIRQGate(apic->cores[cpuNum].cpu_IDT, (APIC_IRQ_ERROR - HW_IRQ_BASE), (uintptr_t)IntrDefaultGates[APIC_IRQ_ERROR]))
 271                 {
 272                     krnPanic(NULL, "Failed to set APIC Error IRQ Vector\n"
 273                                    "IRQ #$%02X, Vector #$%02X\n", (APIC_IRQ_ERROR - HW_IRQ_BASE), APIC_IRQ_ERROR);
 274                 }
 275             }
 276             else if (!core_SetIDTGate((apicidt_t *)apic->cores[cpuNum].cpu_IDT, APIC_IRQ_ERROR, (uintptr_t)IntrDefaultGates[APIC_IRQ_ERROR], TRUE))
 277             {
 278                 krnPanic(NULL, "Failed to set APIC Error Vector\n"
 279                                "Vector #$%02X\n", APIC_IRQ_ERROR);
 280             }
 281             else if (cpuNum == 0)
 282                 KrnAddExceptionHandler((APIC_IRQ_ERROR - APIC_IRQ_COUNT), core_APICErrorHandle, NULL, NULL);
 283
 284             D(bug("[Kernel:APIC-IA32.%03u] %s: APIC Error Vector #$%02X configured\n", cpuNum, __func__, APIC_IRQ_ERROR));
 285
 286             if (ssp)
 287                 UserState(ssp);
 288         }
 289         else
 290         {
 291             krnPanic(NULL, "Failed to configure APIC\n"
 292                                "APIC #%03e ID %03u\n", cpuNum, apic->cores[cpuNum].cpu_LocalID);
 293         }
 294
 295         /* Use flat interrupt model with logical destination ID = 1 */
 296         APIC_REG(__APICBase, APIC_DFR) = DFR_FLAT;
 297         APIC_REG(__APICBase, APIC_LDR) = 1 << LDR_ID_SHIFT;
 298
 299         /* Set Task Priority to 'accept all interrupts' */
 300         APIC_REG(__APICBase, APIC_TPR) = 0;
 301
 302         /* Set spurious IRQ vector to 0xFF. APIC enabled, focus check disabled. */
 303         APIC_REG(__APICBase, APIC_SVR) = SVR_ASE|SVR_FCC|0xFF;
 304
 305         /*
 306          * Set LINT0 to external and LINT1 to NMI.
 307          * These are common defaults and they are going to be overriden by ACPI tables.
 308          */
 309         APIC_REG(__APICBase, APIC_LINT0_VEC) = LVT_MT_EXT;
 310         APIC_REG(__APICBase, APIC_LINT1_VEC) = LVT_MT_NMI;
 311
 312 #ifdef CONFIG_LEGACY
 313         /* Due to the Pentium erratum 3AP. */
 314         if (maxlvt > 3)
 315              APIC_REG(__APICBase, APIC_ESR) = 0;
 316 #endif
 317
 318         D(bug("[Kernel:APIC-IA32.%03u] %s: APIC ESR before enabling vector: %08x\n", cpuNum, __func__, APIC_REG(__APICBase, APIC_ESR)));
 319
 320         /* Set APIC error interrupt to fixed vector interrupt "APIC_IRQ_ERROR",  on APIC error */
 321         APIC_REG(__APICBase, APIC_ERROR_VEC) = APIC_IRQ_ERROR;
 322
 323         /* spec says clear errors after enabling vector. */
 324         if (maxlvt > 3)
 325              APIC_REG(__APICBase, APIC_ESR) = 0;
 326
 327         D(bug("[Kernel:APIC-IA32.%03u] %s: APIC ESR after enabling vector: %08x\n", cpuNum, __func__, APIC_REG(__APICBase, APIC_ESR)));
 328
 329         /*
 330          * Now the tricky thing - calibrate LAPIC timer frequency.
 331          * In fact we could simply query CPU's clock frequency, but... x86 sucks. There's no
 332          * unified way to get it on whatever CPU. Intel has own way, AMD has own way... Etc... Which, additionally,
 333          * varies between CPU generations.
 334          *
 335          * The idea behing the calibration is to run the timer once, and see how much ticks passes in some defined
 336          * period of time. Then calculate a proportion.
 337          * We use 8253 PIT as our reference.
 338          * This calibrarion algorighm is based on NetBSD one.
 339          */
 340
 341         /* Set the timer to one-shot mode, no interrupt, 1:1 divisor */
 342         APIC_REG(__APICBase, APIC_TIMER_VEC) = LVT_MASK;
 343         APIC_REG(__APICBase, APIC_TIMER_DIV) = TIMER_DIV_1;
 344         APIC_REG(__APICBase, APIC_TIMER_ICR) = 0x80000000;      /* Just some very large value */
 345
 346         /*
 347          * Now wait for 11931 PIT ticks, which is equal to 10 milliseconds.
 348          * We don't use pit_udelay() here, because for improved accuracy we need to sample LAPIC timer counter twice,
 349          * before and after our actual delay (PIT setup also takes up some time, so LAPIC will count away from its
 350          * initial value).  We run it 5 times to make up for cache setup discrepancies.
 351          */
 352         for (i = 0; i < 5; i ++)
 353         {
 354             pit_start(11931);
 355             lapic_initial = (LONG)APIC_REG(__APICBase, APIC_TIMER_CCR);
 356
 357             pit_final   = pit_wait(11931);
 358             lapic_final = (LONG)APIC_REG(__APICBase, APIC_TIMER_CCR);
 359             calibrated += (((QUAD)(lapic_initial - lapic_final) * 11931LL)/(11931LL - (QUAD)pit_final)) ;
 360         }
 361         apic->cores[cpuNum].cpu_TimerFreq = 20 * calibrated;
 362         D(bug("[Kernel:APIC-IA32.%03u] %s: LAPIC frequency should be %u Hz (%u MHz)\n", cpuNum, __func__, apic->cores[cpuNum].cpu_TimerFreq, (apic->cores[cpuNum].cpu_TimerFreq + 500000) / 1000000));
 363
 364 #if (0)
 365         /*
 366          * Once APIC timer has been calibrated -:
 367          * # set it to run at it's full
 368          * # reload every second.
 369          * # Enable the heartbeat vector
 370          */
 371         if (cpuNum == 0)
 372         {
 373             if (krnInitInterrupt(KernelBase, (APIC_IRQ_HEARTBEAT - HW_IRQ_BASE), APICInt_IntrController.ic_Node.ln_Type, 0))
 374             {
 375                 struct IntrNode *hbHandle;
 376
 377                 hbHandle = krnAllocIntrNode();
 378                 D(bug("[Kernel:APIC-IA32.%03u] %s: heartbeat handler @ 0x%p\n", cpuNum, __func__, hbHandle));
 379
 380                 if (hbHandle)
 381                 {
 382                     hbHandle->in_Handler = APICHeartbeatServer;
 383                     hbHandle->in_HandlerData = NULL;
 384                     hbHandle->in_HandlerData2 = NULL;
 385                     hbHandle->in_type = it_interrupt;
 386                     hbHandle->in_nr = APIC_IRQ_HEARTBEAT - HW_IRQ_BASE;
 387
 388                     Disable();
 389                     ADDHEAD(&KERNELIRQ_LIST(hbHandle->in_nr), &hbHandle->in_Node);
 390                     Enable();
 391
 392                     apic->flags |= APF_TIMER;
 393                 }
 394                 else
 395                 {
 396                     D(bug("[Kernel:APIC-IA32.%03u] %s: failed to allocate HeartBeat handler\n", cpuNum, __func__);)
 397                 }
 398             }
 399             else
 400             {
 401                 D(bug("[Kernel:APIC-IA32.%03u] %s: failed to obtain HeartBeat IRQ %d\n", cpuNum, __func__, (APIC_IRQ_HEARTBEAT - HW_IRQ_BASE));)
 402             }
 403         }
 404 #endif
 405
 406         if ((apic->flags & APF_TIMER) &&
 407             ((KrnIsSuper()) || ((ssp = SuperState()) != NULL)))
 408         {
 409             if (!core_SetIDTGate(apic->cores[cpuNum].cpu_IDT, APIC_IRQ_HEARTBEAT, (uintptr_t)IntrDefaultGates[APIC_IRQ_HEARTBEAT], FALSE))
 410             {
 411                 krnPanic(NULL, "Failed to set APIC HeartBeat IRQ Vector\n"
 412                                "IRQ #$%02X, Vector #$%02X\n", (APIC_IRQ_HEARTBEAT - HW_IRQ_BASE), APIC_IRQ_HEARTBEAT);
 413             }
 414             APIC_REG(__APICBase, APIC_TIMER_VEC) = APIC_IRQ_HEARTBEAT | LVT_TMM_PERIOD;
 415             APIC_REG(__APICBase, APIC_TIMER_DIV) = TIMER_DIV_1;
 416             APIC_REG(__APICBase, APIC_TIMER_CCR) = apic->cores[cpuNum].cpu_TimerFreq;
 417             APIC_REG(__APICBase, APIC_TIMER_ICR) = apic->cores[cpuNum].cpu_TimerFreq;
 418
 419             ictl_enable_irq((APIC_IRQ_HEARTBEAT - HW_IRQ_BASE), KernelBase);
 420
 421             if (ssp)
 422                 UserState(ssp);
 423         }
 424         else
 425         {
 426             APIC_REG(__APICBase, APIC_TIMER_VEC) = LVT_MASK | LVT_TMM_PERIOD;
 427             APIC_REG(__APICBase, APIC_TIMER_DIV) = TIMER_DIV_1;
 428             APIC_REG(__APICBase, APIC_TIMER_CCR) = apic->cores[cpuNum].cpu_TimerFreq;
 429             APIC_REG(__APICBase, APIC_TIMER_ICR) = apic->cores[cpuNum].cpu_TimerFreq;
 430         }
 431     }
 432 }
 433
 434 apicid_t core_APIC_GetID(IPTR _APICBase)
 435 {
 436     apicid_t _apic_id;
 437
 438     /* The actual ID is in 8 most significant bits */
 439     _apic_id = APIC_REG(_APICBase, APIC_ID) >> APIC_ID_SHIFT;
 440     DID(bug("[Kernel:APIC-IA32] %s: %03u\n", __func__, _apic_id));
 441
 442     return _apic_id;
 443 }
 444
 445 ULONG core_APIC_Wake(APTR wake_apicstartrip, apicid_t wake_apicid, IPTR __APICBase)
 446 {
 447     ULONG status_ipisend, status_ipirecv;
 448     ULONG start_count;
 449 #ifdef CONFIG_LEGACY
 450     ULONG apic_ver = APIC_REG(__APICBase, APIC_VERSION);
 451 #endif
 452     D(
 453         apicid_t cpuNo = KrnGetCPUNumber();
 454
 455         bug("[Kernel:APIC-IA32.%03u] %s(%03u @ %p)\n", cpuNo, __func__, wake_apicid, wake_apicstartrip);
 456         bug("[Kernel:APIC-IA32.%03u] %s: Base @ %p\n", cpuNo, __func__, __APICBase);
 457     )
 458 #ifdef CONFIG_LEGACY
 459     /*
 460      * Check if we have old 82489DX discrete APIC (version & 0xF0 == 0).
 461      * This APIC needs different startup procedure. It doesn't support STARTUP IPI
 462      * because old CPUs didn't have INIT signal. They jump to BIOS ROM boot code
 463      * immediately after INIT IPI. In order to run the bootstrap, a BIOS warm reset
 464      * magic has to be used there.
 465      */
 466     if (!APIC_INTEGRATED(apic_ver))
 467     {
 468         /*
 469          * BIOS warm reset magic, part one.
 470          * Write real-mode bootstrap routine address to 40:67 (real-mode address) location.
 471          * This is standard feature of IBM PC AT BIOS. If a warm reset condition is detected,
 472          * the BIOS jumps to the given address.
 473          */
 474         D(bug("[Kernel:APIC-IA32.%03u] %s: Setting BIOS vector for trampoline @ %p ..\n", cpuNo, __func__, wake_apicstartrip));
 475         *((volatile unsigned short *)0x469) = (IPTR)wake_apicstartrip >> 4;
 476         *((volatile unsigned short *)0x467) = 0; /* Actually wake_apicstartrip & 0x0F, it's page-aligned. */
 477
 478         /*
 479          * BIOS warm reset magic, part two.
 480          * This writes 0x0A into CMOS RAM, location 0x0F. This signals a warm reset condition to BIOS,
 481          * making part one work.
 482          */
 483         D(bug("[Kernel:APIC-IA32.%03u] %s: Setting warm reset code ..\n", cpuNo, __func__));
 484         outb(0xf, 0x70);
 485         outb(0xa, 0x71);
 486     }
 487 #endif
 488
 489     /* Flush TLB (we are supervisor here) */
 490     wrcr(cr3, rdcr(cr3));
 491
 492     /* First we send the INIT command (reset the core). Vector must be zero for this. */
 493     status_ipisend = DoIPI(__APICBase, wake_apicid, ICR_INT_LEVELTRIG | ICR_INT_ASSERT | ICR_DM_INIT);
 494     if (status_ipisend)
 495     {
 496         D(bug("[Kernel:APIC-IA32.%03u] %s: Error asserting INIT\n", cpuNo, __func__));
 497         return status_ipisend;
 498     }
 499
 500     /* Deassert INIT after a small delay */
 501     pit_udelay(10 * 1000);
 502
 503     /* Deassert INIT */
 504     status_ipisend = DoIPI(__APICBase, wake_apicid, ICR_INT_LEVELTRIG | ICR_DM_INIT);
 505     if (status_ipisend)
 506     {
 507         D(bug("[Kernel:APIC-IA32.%03u] %s: Error deasserting INIT\n", cpuNo, __func__));
 508         return status_ipisend;
 509     }
 510
 511     /* memory barrier */
 512     asm volatile("mfence":::"memory");
 513
 514 #ifdef CONFIG_LEGACY
 515     /* If it's 82489DX, we are done. */
 516     if (!APIC_INTEGRATED(apic_ver))
 517     {
 518         DWAKE(bug("[Kernel:APIC-IA32.%03u] %s: 82489DX detected, wakeup done\n", cpuNo, __func__));
 519         return 0;
 520     }
 521 #endif
 522
 523     /*
 524      * Perform IPI STARTUP loop.
 525      * According to official Intel specification, this must be done twice.
 526      * It's not explained why. ;-)
 527      */
 528     for (start_count = 1; start_count <= 2; start_count++)
 529     {
 530         D(bug("[Kernel:APIC-IA32.%03u] %s: Attempting STARTUP .. %u\n", cpuNo, __func__, start_count));
 531
 532         /* Clear any pending error condition */
 533         APIC_REG(__APICBase, APIC_ESR) = 0;
 534
 535         /*
 536          * Send STARTUP IPI.
 537          * The processor starts up at CS = (vector << 16) and IP = 0.
 538          */
 539         status_ipisend = DoIPI(__APICBase, wake_apicid, ICR_DM_STARTUP | ((IPTR)wake_apicstartrip >> 12));
 540
 541         /* Allow the target APIC to accept the IPI */
 542         pit_udelay(200);
 543
 544 #ifdef CONFIG_LEGACY
 545         /* Pentium erratum 3AP quirk */
 546         if (APIC_LVT(apic_ver) > 3)
 547             APIC_REG(__APICBase, APIC_ESR) = 0;
 548 #endif
 549
 550         status_ipirecv = APIC_REG(__APICBase, APIC_ESR) & 0xEF;
 551
 552         /*
 553          * EXPERIMENTAL:
 554          * On my machine (macmini 3,1, as OS X system profiler says), the core starts up from first
 555          * attempt. The second attempt ends up in error (according to the documentation, the STARTUP
 556          * can be accepted only once, while the core in RESET or INIT state, and first STARTUP, if
 557          * successful, brings the core out of this state).
 558          * Here we try to detect this condition. If the core accepted STARTUP, we suggest that it has
 559          * started up, and break the loop.
 560          * A topic at osdev.org forum (http://forum.osdev.org/viewtopic.php?f=1&t=23018)
 561          * also tells about some problems with double STARTUP. According to it, the second STARTUP can
 562          * manage to re-run the core from the given address, leaving it in 64-bit mode, causing it to crash.
 563          *
 564          * If startup problems pops up (the core doesn't respond and AROS halts at "Launching APIC no X" stage),
 565          * the following two variations of this algorithm can be tried:
 566          * a) Always send STARTUP twice, but signal error condition only if both attempts failed.
 567          * b) Send first STARTUP, abort on error. Allow second attempt to fail and ignore its result.
 568          *
 569          *                                                              Sonic <pavel_fedin@mail.ru>
 570          */
 571         if (!status_ipisend && !status_ipirecv)
 572             break;
 573     }
 574
 575     DWAKE(bug("[Kernel:APIC-IA32.%03u] %s: STARTUP run status 0x%08X, error 0x%08X\n", cpuNo, __func__, status_ipisend, status_ipirecv));
 576
 577     /*
 578      * We return nonzero on error.
 579      * Actually least significant byte of this value holds ESR value, and 12th bit
 580      * holds delivery status flag from DoIPI() routine. It will be '1' if we got
 581      * stuck at sending phase.
 582      */
 583     return (status_ipisend | status_ipirecv);
 584 }