1 #include <proto/exec.h>
2 #include <resources/processor.h>
4 #include <proto/processor.h>
6 APTR ProcessorBase
= NULL
;
8 static ULONG
getcpucount()
11 struct TagItem tags
[] =
13 {GCIT_NumberOfProcessors
, (IPTR
)&cpucount
},
19 printf("CPU Count: %d\n", cpucount
);
30 { VECTORTYPE_NONE
, "None"},
31 { VECTORTYPE_ALTIVEC
, "AltiVec"},
32 { VECTORTYPE_VMX
, "VMX"},
33 { VECTORTYPE_MMX
, "MMX"},
34 { VECTORTYPE_SSE
, "SSE"},
35 { VECTORTYPE_SSE2
, "SSE2"},
36 { VECTORTYPE_SSE3
, "SSE3"},
37 { VECTORTYPE_SSSE3
, "SSSE3"},
38 { VECTORTYPE_SSE41
, "SSE41"},
39 { VECTORTYPE_SSE42
, "SSE42"},
40 { VECTORTYPE_MMXEXT
, "MMX Ext"},
41 { VECTORTYPE_3DNOW
, "3DNow"},
42 { VECTORTYPE_3DNOWEXT
, "3DNow Ext"},
43 { VECTORTYPE_SSE4A
, "SSE4A"},
51 } ProcessorFeatures
[] =
53 { GCIT_SupportsFPU
, "FPU" },
54 { GCIT_SupportsAltiVec
, "AltiVec" },
55 { GCIT_SupportsVMX
, "VMX" },
56 { GCIT_SupportsMMX
, "MMX" },
57 { GCIT_SupportsMMXEXT
, "AMD MMX Entensions" },
58 { GCIT_Supports3DNOW
, "3DNow!" },
59 { GCIT_Supports3DNOWEXT
, "AMD 3DNow! Extensions" },
60 { GCIT_SupportsSSE
, "SSE" },
61 { GCIT_SupportsSSE2
, "SSE2" },
62 { GCIT_SupportsSSE3
, "SSE3" },
63 { GCIT_SupportsSSSE3
, "SSSE3" },
64 { GCIT_SupportsSSE41
, "SSE4.1" },
65 { GCIT_SupportsSSE42
, "SSE4.2" },
66 { GCIT_SupportsSSE4A
, "SSE4a" },
67 { GCIT_SupportsVME
, "Virtual Mode Extension" },
68 { GCIT_SupportsPSE
, "Page Size Extension" },
69 { GCIT_SupportsPAE
, "Physical Address Extension" },
70 { GCIT_SupportsCX8
, "CMPXCHG8 Instruction" },
71 { GCIT_SupportsAPIC
, "APIC" },
72 { GCIT_SupportsCMOV
, "Conditional Move Instruction" },
73 { GCIT_SupportsPSE36
, "36-bit Page Size Extension" },
74 { GCIT_SupportsCLFSH
, "CLFLUSH Instruction" },
75 { GCIT_SupportsACPI
, "ACPI" },
76 { GCIT_SupportsFXSR
, "FXSAVE and FXSTOR Instructions" },
77 { GCIT_SupportsHTT
, "Hyper-Threading Technology" },
78 { GCIT_SupportsCX16
, "CMPXCHG16B Instruction" },
79 { GCIT_SupportsVirtualization
, "Virtualization Technology" },
80 { GCIT_SupportsNoExecutionBit
, "No-Execution Page Bit" },
81 { GCIT_Supports64BitMode
, "64-bit Capable (x86-64)" },
89 } ProcessorArchitecture
[] =
91 { PROCESSORARCH_UNKNOWN
, "Unknown" },
92 { PROCESSORARCH_M68K
, "Motorola 68K" },
93 { PROCESSORARCH_PPC
, "PowerPC" },
94 { PROCESSORARCH_X86
, "X86" },
95 { PROCESSORARCH_ARM
, "ARM" },
103 } CurrentEndianness
[] =
105 { ENDIANNESS_UNKNOWN
, "Unknown" },
106 { ENDIANNESS_LE
, "LE" },
107 { ENDIANNESS_BE
, "BE" },
111 static void printcpuinformation(ULONG index
)
113 TEXT modelstring
[128] = {0};
114 TEXT familystring
[64] = {0};
115 ULONG family
, vectorunit
;
117 ULONG l1size
, l1datasize
, l1instrsize
, l2size
, l3size
, cachelinesize
;
118 ULONG architecture
, endianness
;
120 struct TagItem tags
[] =
122 {GCIT_SelectedProcessor
, index
},
123 {GCIT_ModelString
, (IPTR
)modelstring
},
124 {GCIT_Family
, (IPTR
)&family
},
125 {GCIT_FamilyString
, (IPTR
)familystring
},
126 {GCIT_VectorUnit
, (IPTR
)&vectorunit
},
127 {GCIT_L1CacheSize
, (IPTR
)&l1size
},
128 {GCIT_L1DataCacheSize
, (IPTR
)&l1datasize
},
129 {GCIT_L1InstructionCacheSize
, (IPTR
)&l1instrsize
},
130 {GCIT_L2CacheSize
, (IPTR
)&l2size
},
131 {GCIT_L3CacheSize
, (IPTR
)&l3size
},
132 {GCIT_CacheLineSize
, (IPTR
)&cachelinesize
},
133 {GCIT_Architecture
, (IPTR
)&architecture
},
134 {GCIT_Endianness
, (IPTR
)&endianness
},
140 printf("CPU: %d\n", index
);
141 printf("Family: %d\n", family
);
142 printf("FamilyString: %s\n", familystring
);
143 printf("ModelString: %s\n", modelstring
);
145 while(VectorUnit
[i
].Description
!= NULL
)
147 if (VectorUnit
[i
].VectorUnitType
== vectorunit
)
149 printf("Vector Unit: %s\n", VectorUnit
[i
].Description
);
156 while(ProcessorArchitecture
[i
].Description
!= NULL
)
158 if (ProcessorArchitecture
[i
].Architecture
== architecture
)
160 printf("Architecture: %s\n", ProcessorArchitecture
[i
].Description
);
167 while(CurrentEndianness
[i
].Description
!= NULL
)
169 if (CurrentEndianness
[i
].Endianness
== endianness
)
171 printf("Endianness: %s\n", CurrentEndianness
[i
].Description
);
177 printf("L1CacheSize: %d kB\n", l1size
);
178 printf("L1DataCacheSize: %d kB\n", l1datasize
);
179 printf("L1InstructionCacheSize: %d kB\n", l1instrsize
);
180 printf("L2CacheSize: %d kB\n", l2size
);
181 printf("L3CacheSize: %d kB\n", l3size
);
182 printf("CacheLineSize: %d B\n", cachelinesize
);
184 printf("Features:\n");
186 while(ProcessorFeatures
[i
].Description
!= NULL
)
189 struct TagItem ftags
[] =
191 { GCIT_SelectedProcessor
, index
},
192 { ProcessorFeatures
[i
].Feature
, (IPTR
)&check
},
193 { TAG_DONE
, TAG_DONE
}
199 printf(" [%s]\n", ProcessorFeatures
[i
].Description
);
209 if ((ProcessorBase
= OpenResource(PROCESSORNAME
)) == NULL
)
211 printf("Not able to open %s\n", PROCESSORNAME
);
215 cpus
= getcpucount();
217 for(index
= 0; index
< cpus
; index
++)
218 printcpuinformation(index
);