Added chip revision constant
[AROS.git] / arch / arm-sun4i / include / hardware / tmr.h
blob3540208a1eee788754092aedbbc4465b83955372
1 /*
2 Copyright © 2014, The AROS Development Team. All rights reserved.
3 $Id$
5 Desc: sun4i timer module
6 Lang: english
7 */
9 #ifndef HARDWARE_SUN4I_TIMER_H
10 #define HARDWARE_SUN4I_TIMER_H
12 #ifndef EXEC_TYPES_H
13 #include <exec/types.h>
14 #endif
16 #ifndef _INTTYPES_H
17 #include <inttypes.h>
18 #endif
20 #define SUN4I_TIMER_BASE 0x01c20c00
22 #define TIMER_IRQ_EN (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0000))
23 #define TIMER_IRQ_STA (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0004))
24 #define TIMER0_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0010))
25 #define TIMER0_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0014))
26 #define TIMER0_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0018))
27 #define TIMER1_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0020))
28 #define TIMER1_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0024))
29 #define TIMER1_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0028))
30 #define TIMER2_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0030))
31 #define TIMER2_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0034))
32 #define TIMER2_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0038))
33 #define TIMER3_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0040))
34 #define TIMER3_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0044))
35 #define TIMER3_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0048))
36 #define TIMER4_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0050))
37 #define TIMER4_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0054))
38 #define TIMER4_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0058))
39 #define TIMER5_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0060))
40 #define TIMER5_INTR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0064))
41 #define TIMER5_CUR_VAL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0068))
42 #define TIMER_AVS_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0080))
43 #define TIMER_AVS0 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0084))
44 #define TIMER_AVS1 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0088))
45 #define TIMER_AVS_DIV (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x008c))
46 #define TIMER_WDT_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0090))
47 #define TIMER_WDT_MODE (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0094))
48 #define TIMER_CNT64_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x00a0))
49 #define TIMER_CNT64_LO (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x00a4))
50 #define TIMER_CNT64_HI (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x00a8))
51 #define TIMER_32KHZ_OSC_CTRL (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0100))
52 #define TIMER_RTC_DATE (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0104))
53 #define TIMER_RTC_TIME (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0108))
54 #define TIMER_ALARM_CNT (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x010c))
55 #define TIMER_ALARM_WK (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0110))
56 #define TIMER_ALARM_EN (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0114))
57 #define TIMER_ALARM_IRQ_EN (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0118))
58 #define TIMER_ALARM_IRQ_STA (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x011c))
59 #define TIMER_GP0 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0120))
60 #define TIMER_GP1 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0124))
61 #define TIMER_GP2 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x0128))
62 #define TIMER_GP3 (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x012c))
63 #define TIMER_CPU_CFG (*(volatile uint32_t *)(SUN4I_TIMER_BASE + 0x013c)) // A10 user manual has this wrong!
65 #define TIMER_CPU_CFG_CHIP_REV_A 0
66 #define TIMER_CPU_CFG_CHIP_REV_C1 1
67 #define TIMER_CPU_CFG_CHIP_REV_C2 2
68 #define TIMER_CPU_CFG_CHIP_REV_B 3
70 #endif