rom/hidds/hidd.pci/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 /*
   5     Copyright © 2004-2013, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 #include <exec/types.h>
  10 #include <exec/libraries.h>
  11 #include <exec/execbase.h>
  12 #include <exec/nodes.h>
  13 #include <exec/lists.h>
  14 #include <exec/semaphores.h>
  15 #include <dos/bptr.h>
  16
  17 #include <aros/libcall.h>
  18 #include <aros/asmcall.h>
  19
  20 #include <oop/oop.h>
  21
  22 #include <exec/execbase.h>
  23
  24 #include LC_LIBDEFS_FILE
  25
  26 /* Private data and structures unavailable outside the pci base classes */
  27
  28 struct DrvInstData {
  29     BOOL DirectBus;
  30     IPTR IOBase;
  31 };
  32
  33 typedef struct DeviceData {
  34     struct MinNode      node;           /* Accessed directly by PCI subsystem class */
  35     OOP_Object          *driver;
  36     UBYTE               bus,dev,sub;
  37     UBYTE               isBridge;
  38     UBYTE               subbus;
  39     UWORD               VendorID;
  40     UWORD               ProductID;
  41     UBYTE               RevisionID;
  42     UBYTE               Interface;
  43     UBYTE               SubClass;
  44     UBYTE               Class;
  45     UWORD               SubsysVID;
  46     UWORD               SubsystemID;
  47     UBYTE               INTLine;
  48     UBYTE               IRQLine;
  49     UBYTE               HeaderType;
  50     struct {
  51         IPTR            addr;
  52         IPTR            size;
  53     } BaseReg[6];
  54     ULONG               RomBase;
  55     ULONG               RomSize;
  56
  57     STRPTR              strClass;
  58     STRPTR              strSubClass;
  59     STRPTR              strInterface;
  60
  61     struct SignalSemaphore ownerLock;
  62 } tDeviceData;
  63
  64 struct pci_staticdata {
  65     struct SignalSemaphore dev_lock;
  66     struct MinList      devices;        /* List of devices */
  67
  68     APTR                kernelBase;
  69     struct Library      *utilityBase;
  70     struct Library      *oopBase;
  71
  72     OOP_AttrBase        hwAttrBase;
  73     OOP_AttrBase        hiddPCIAB;
  74     OOP_AttrBase        hiddPCIDriverAB;
  75     OOP_AttrBase        hiddPCIBusAB;
  76     OOP_AttrBase        hiddPCIDeviceAB;
  77     OOP_MethodID        hiddPCIDriverMB;
  78     OOP_MethodID        hwMethodBase;
  79
  80     OOP_Class           *pciClass;
  81     OOP_Class           *pciDeviceClass;
  82     OOP_Class           *pciDriverClass;
  83     OOP_Object          *pciObject;
  84
  85     BPTR                segList;
  86 };
  87
  88 struct pcibase {
  89     struct Library              LibNode;
  90     struct pci_staticdata       psd;
  91 };
  92
  93 OOP_Class *init_pcideviceclass(struct pci_staticdata *);
  94 void free_pcideviceclass(struct pci_staticdata *, OOP_Class *cl);
  95
  96 #define BASE(lib) ((struct pcibase*)(lib))
  97
  98 #define PSD(cl) (&BASE(cl->UserData)->psd)
  99
 100 /*
 101     There are no static AttrBases in this class. Therefore it might be placed
 102     directly in ROM without any harm
 103 */
 104 #undef HiddPCIAttrBase
 105 #undef HiddPCIDeviceAttrBase
 106 #undef HiddPCIDriverAttrBase
 107 #undef HWAttrBase
 108 #undef HiddPCIDriverBase
 109 #undef HWBase
 110
 111 #define HiddPCIAttrBase       (PSD(cl)->hiddPCIAB)
 112 #define HiddPCIDeviceAttrBase (PSD(cl)->hiddPCIDeviceAB)
 113 #define HiddPCIDriverAttrBase (PSD(cl)->hiddPCIDriverAB)
 114 #define HWAttrBase            (PSD(cl)->hwAttrBase)
 115 #define HiddPCIDriverBase     (PSD(cl)->hiddPCIDriverMB)
 116 #define HWBase                (PSD(cl)->hwMethodBase)
 117
 118 #define KernelBase (PSD(cl)->kernelBase)
 119 #define UtilityBase PSD(cl)->utilityBase
 120 #define OOPBase     PSD(cl)->oopBase
 121
 122 /* PCI Configspace offsets */
 123 #define PCICS_VENDOR        0x00
 124 #define PCICS_PRODUCT       0x02
 125 #define PCICS_COMMAND       0x04
 126 #define PCICS_STATUS        0x06
 127 #define PCICS_REVISION      0x08
 128 #define PCICS_PROGIF        0x09
 129 #define PCICS_SUBCLASS      0x0a
 130 #define PCICS_CLASS         0x0b
 131 #define PCICS_CACHELS       0x0c
 132 #define PCICS_LATENCY       0x0d
 133 #define PCICS_HEADERTYPE    0x0e
 134 #define PCICS_BIST          0x0f
 135 #define PCICS_BAR0          0x10
 136 #define PCICS_BAR1          0x14
 137 #define PCICS_BAR2          0x18
 138 #define PCICS_BAR3          0x1c
 139 #define PCICS_BAR4          0x20
 140 #define PCICS_BAR5          0x24
 141 #define PCICS_CARDBUS_CIS   0x28
 142 #define PCICS_SUBVENDOR     0x2c
 143 #define PCICS_SUBSYSTEM     0x2e
 144 #define PCICS_EXPROM_BASE   0x30
 145 #define PCICS_CAP_PTR       0x34
 146 #define PCICS_INT_LINE      0x3c
 147 #define PCICS_INT_PIN       0x3d
 148 #define PCICS_MIN_GNT       0x3e
 149 #define PCICS_MAX_LAT       0x3f
 150
 151 /* PCI Headertypes */
 152 #define PCIHT_MASK          0x7f
 153 #define PCIHT_MULTIFUNC     0x80
 154
 155 #define PCIHT_NORMAL        0x00
 156 #define PCIHT_BRIDGE        0x01
 157 #define PCIHT_CARDBUS       0x02
 158
 159 /* PCI Command register bits */
 160 #define PCICMB_IODECODE     0
 161 #define PCICMB_MEMDECODE    1
 162 #define PCICMB_BUSMASTER    2
 163 #define PCICMB_SPECIAL      3
 164 #define PCICMB_INVALIDATE   4
 165 #define PCICMB_VGASNOOP     5
 166 #define PCICMB_PARITY       6
 167 #define PCICMB_STEPPING     7
 168 #define PCICMB_SERR         8
 169 #define PCICMB_FASTB2B      9
 170
 171 #define PCICMF_IODECODE     (1 << PCICMB_IODECODE)
 172 #define PCICMF_MEMDECODE    (1 << PCICMB_MEMDECODE)
 173 #define PCICMF_BUSMASTER    (1 << PCICMB_BUSMASTER)
 174 #define PCICMF_SPECIAL      (1 << PCICMB_SPECIAL)
 175 #define PCICMF_INVALIDATE   (1 << PCICMB_INVALIDATE)
 176 #define PCICMF_VGASNOOP     (1 << PCICMB_VGASNOOP)
 177 #define PCICMF_PARITY       (1 << PCICMB_PARITY)
 178 #define PCICMF_STEPPING     (1 << PCICMB_STEPPING)
 179 #define PCICMF_SERR         (1 << PCICMB_SERR)
 180 #define PCICMF_FASTB2B      (1 << PCICMB_FASTB2B)
 181
 182 /* PCI Status register bits */
 183 #define PCISTB_INTERRUPT_STATUS 3       /* might be AHCI specific */
 184 #define PCISTB_CAPABILITES      4
 185 #define PCISTB_66MHZ            5
 186 #define PCISTB_FASTB2B          7
 187 #define PCISTB_PARITY           8
 188 #define PCISTB_SIG_TGT_ABORT    11
 189 #define PCISTB_REC_TGT_ABORT    12
 190 #define PCISTB_REC_MAS_ABORT    13
 191 #define PCISTB_SIG_SYSERR       14
 192 #define PCISTB_PARITYERR        15
 193
 194 #define PCISTF_INTERRUPT_STATUS (1 << PCISTB_INTERRUPT_STATUS)
 195 #define PCISTF_CAPABILITIES     (1 << PCISTB_CAPABILITES)
 196 #define PCISTF_66MHZ            (1 << PCISTB_66MHZ)
 197 #define PCISTF_FASTB2B          (1 << PCISTB_FASTB2B)
 198 #define PCISTF_PARITY           (1 << PCISTB_PARITY)
 199 #define PCISTF_SIG_TGT_ABORT    (1 << PCISTB_SIG_TGT_ABORT)
 200 #define PCISTF_REC_TGT_ABORT    (1 << PCISTB_REC_TGT_ABORT)
 201 #define PCISTF_REC_MAS_ABORT    (1 << PCISTB_REC_MAS_ABORT)
 202 #define PCISTF_SIG_SYSERR       (1 << PCISTB_SIG_SYSERR)
 203 #define PCISTF_PARITYERR        (1 << PCISTB_PARITYERR)
 204
 205 #define PCIST_DEVSEL_MASK   0x600
 206 #define PCIST_DEVSEL_FAST   0x000
 207 #define PCIST_DEVSEL_MEDIUM 0x200
 208 #define PCIST_DEVSEL_SLOW   0x400
 209
 210 /* PCI BIST register */
 211 #define PCIBSB_START            6
 212 #define PCIBSB_CAPABLE          7
 213
 214 #define PCIBSF_START            (1 << PCIBSB_START)
 215 #define PCIBSF_CAPABLE          (1 << PCIBSB_CAPABLE)
 216
 217 #define PCIBS_CODEMASK          0x0f
 218
 219 /* PCI BaseAddressRegister defines */
 220 #define PCIBAR_MASK_TYPE        0x01
 221 #define PCIBAR_TYPE_MMAP        0x00
 222 #define PCIBAR_TYPE_IO          0x01
 223 #define PCIBAR_MASK_MEM         0xfffffff0
 224 #define PCIBAR_MASK_IO          0xfffffffc
 225
 226 #define PCIBAR_MEMTYPE_MASK     0x06
 227 #define PCIBAR_MEMTYPE_32BIT    0x00
 228 #define PCIBAR_MEMTYPE_64BIT    0x04
 229
 230 #define PCIBARB_PREFETCHABLE    3
 231 #define PCIBARF_PREFETCHABLE    (1 << PCIBARB_PREFETCHABLE)
 232
 233 /*
 234  * PCI-to-PCI bridge header defines
 235  * First 16 bytes are the same as normal PCI dev
 236  * Use either PCICS_ or PCIBR_ prefix
 237  */
 238 #define PCIBR_VENDOR        PCICS_VENDOR
 239 #define PCIBR_PRODUCT       PCICS_PRODUCT
 240 #define PCIBR_COMMAND       PCICS_COMMAND
 241 #define PCIBR_STATUS        PCICS_STATUS
 242 #define PCIBR_REVISION      PCICS_REVISION
 243 #define PCIBR_PROGIF        PCICS_PROGIF
 244 #define PCIBR_SUBCLASS      PCICS_SUBCLASS
 245 #define PCIBR_CLASS         PCICS_CLASS
 246 #define PCIBR_CACHELS       PCICS_CACHELS
 247 #define PCIBR_LATENCY       PCICS_LATENCY
 248 #define PCIBR_HEADERTYPE    PCICS_HEADERTYPE
 249 #define PCIBR_BIST          PCICS_BIST
 250 #define PCIBR_BAR0          0x10
 251 #define PCIBR_BAR1          0x14
 252 #define PCIBR_PRIBUS        0x18
 253 #define PCIBR_SECBUS        0x19
 254 #define PCIBR_SUBBUS        0x1a
 255 #define PCIBR_SECLATENCY    0x1b
 256 #define PCIBR_IOBASE        0x1c
 257 #define PCIBR_IOLIMIT       0x1d
 258 #define PCIBR_SECSTATUS     0x1e
 259 #define PCIBR_MEMBASE       0x20
 260 #define PCIBR_MEMLIMIT      0x22
 261 #define PCIBR_PREFETCHBASE  0x24
 262 #define PCIBR_PREFETCHLIMIT 0x26
 263 #define PCIBR_PREBASEUPPER  0x28
 264 #define PCIBR_PRELIMITUPPER 0x2c
 265 #define PCIBR_IOBASEUPPER   0x30
 266 #define PCIBR_IOLIMITUPPER  0x32
 267 #define PCIBR_CAPPTR        0x34
 268 #define PCIBR_EXPROMBASE    0x38
 269 #define PCIBR_INT_LINE      0x3c
 270 #define PCIBR_INT_PIN       0x3d
 271 #define PCIBR_CONTROL       0x3e
 272
 273 #define PCICTRLB_ISAENABLE      2
 274 #define PCICTRLB_VGAENABLE      3
 275
 276 #define PCICTRLF_ISAENABLE          (1 << PCICTRLB_ISAENABLE)
 277 #define PCICTRLF_VGAENABLE          (1 << PCICTRLB_VGAENABLE)
 278
 279 /* PCI capabilities */
 280 #define PCICAP_POWER_MANAGEMENT     0x01
 281 #define PCICAP_AGP                  0x02
 282 #define PCICAP_VITAL_PRODUCT_DATA   0x03
 283 #define PCICAP_SLOT_ID              0x04
 284 #define PCICAP_MSI                  0x05
 285 #define PCICAP_CPCI_HOT_SWAP        0x06
 286 #define PCICAP_PCIX                 0x07
 287 #define PCICAP_HYPER_TRANSPORT      0x08
 288 #define PCICAP_VENDOR_SPECIFIC      0x09
 289 #define PCICAP_DEBUG_PORT           0x0a
 290 #define PCICAP_CPCI_CR              0x0b
 291 #define PCICAP_HOT_PLUG_CONTROLLER  0x0c
 292 #define PCICAP_SSVPID               0x0d
 293 #define PCICAP_AGP3                 0x0e
 294 #define PCICAP_PCIE                 0x10
 295 #define PCICAP_MSIX                 0x11
 296 #define PCICAP_ADVANCED_FEATURES    0x13
 297
 298 /* PCI Express Configspace offsets */
 299 #define PCIECS_VENDOR       PCICS_VENDOR
 300 #define PCIECS_PRODUCT      PCICS_PRODUCT
 301 #define PCIECS_COMMAND      PCICS_COMMAND
 302 #define PCIECS_STATUS       PCICS_STATUS
 303 #define PCIECS_REVISION     PCICS_REVISION
 304 #define PCIECS_PROGIF       PCICS_PROGIF
 305 #define PCIECS_SUBCLASS     PCICS_SUBCLASS
 306 #define PCIECS_CLASS        PCICS_CLASS
 307 #define PCIECS_CACHELS      PCICS_CACHELS
 308 #define PCIECS_LATENCY      PCICS_LATENCY
 309 #define PCIECS_HEADERTYPE   PCICS_HEADERTYPE
 310 #define PCIECS_BIST         PCICS_BIST
 311 #define PCIECS_CAP_PTR      PCICS_CAP_PTR
 312 #define PCIECS_INT_LINE     PCICS_INT_LINE
 313 #define PCIECS_INT_PIN      PCICS_INT_PIN
 314
 315 /* PCI Express capability structure */
 316 #define PCIECS_CAPID        0x00
 317 #define PCIECS_NEXTCAP      0x01
 318 #define PCIECS_PCIECAP      0x02
 319 #define PCIECS_DEVCAP       0x04
 320 #define PCIECS_DEVCTL       0x08
 321 #define PCIECS_DEVSTS       0x0A
 322 #define PCIECS_LINKCAP      0x0C
 323 #define PCIECS_LINKCTL      0x10
 324 #define PCIECS_LINKSTS      0x12
 325 #define PCIECS_SLOTCAP      0x14
 326 #define PCIECS_SLOTCTL      0x18
 327 #define PCIECS_SLOTSTS      0x1A
 328 #define PCIECS_ROOTCTL      0x1C
 329 #define PCIECS_ROOTSTS      0x20
 330 #define PCIECS_DEVCAP2      0x24
 331 #define PCIECS_DEVCTL2      0x28
 332 #define PCIECS_DEVSTS2      0x2A
 333 #define PCIECS_LINKCAP2     0x2C
 334 #define PCIECS_LINKCTL2     0x30
 335 #define PCIECS_LINKSTS2     0x32
 336 #define PCIECS_SLOTCAP2     0x34
 337 #define PCIECS_SLOTCTL2     0x38
 338 #define PCIECS_SLOTSTS2     0x3A
 339
 340 /* PCI Express capabilities */
 341 #define PCIECAP_VER_MASK    0xF
 342 #define PCIECAP_VER_10      0x1 /* PCIe spec 1.0 */
 343 #define PCIECAP_VER_20      0x2 /* PCIe spec 2.0 */
 344
 345 #endif /* _PCI_H */
 346